Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.

Abstract: Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor including receiving a load instruction in a load reorder queue, wherein the load instruction is an instruction to load data from a memory location; subsequent to receiving the load instruction, receiving a store instruction in a store reorder queue, wherein the store instruction is an instruction to store data in the memory location; determining that the store instruction causes a hazard against the load instruction; preventing a flush of the load reorder queue based on a state of the load instruction; and re-executing the load instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the multi-slice processor is configured to dynamically cancel partial load operations by, among other steps, receiving a load instruction requesting multiple portions of data; receiving a load instruction requesting multiple portions of data; determining that a load of one portion of the requested multiple portions is unavailable to be issued; and responsive to determining that the load of the one portion of the requested multiple portions is unavailable to be issued, delaying issuance of the load instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where each load/store slice includes a load miss queue and a load reorder queue, includes: receiving, at a load reorder queue, a load instruction requesting data; responsive to the data not being stored in a data cache, determining whether a previous load instruction is pending a fetch of a cache line comprising the data; if the cache line does not comprise the data, allocating an entry for the load instruction in the load miss queue; and if the cache line does comprise the data: merging, in the load reorder queue, the load instruction with an entry for the previous load instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and an instruction sequencing unit, where operation includes: receiving, at a load/store slice, a load instruction to be issued; determining, at the load/store slice, that the load instruction has not completed and is to be reissued; and responsive to determining that the load instruction is to be reissued, delaying a signal, from the load/store slice to the instruction sequencing unit, that allows the instruction sequencing unit to issue one or more instructions dependent upon the load instruction.

Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.

Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.

Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.

Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.

Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.

Abstract: Method for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination.

Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.

Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.

Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.

Abstract: Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.

Abstract: Method, computer program product, and system for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination.

Abstract: Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.