Abstract: Systems and methods to manage memory refreshes at a memory controller are disclosed. A method includes determining, at a memory controller device, that a number of transmission errors between a memory controller port and a memory redrive device exceeds an error threshold. The method may include initiating a first link retraining process between the memory controller port and the memory redrive device. The method may further include placing one or more dynamic random access memory modules associated with the memory redrive device in a self-refresh mode. The method may also include removing the one or more dynamic random access memory modules from the self-refresh mode after the link retraining process has completed. The method may further include enabling overlapping refreshes of the one or more dynamic random access memory modules.

Abstract: A computer system, computer program product, and method implement dynamic physical memory reallocation. A system management interface (SMI) Handler and an Operating System (OS) are arranged for exchanging communications. Periodically the SMI Handler queries the operating system to identify a percentage of available memory currently being utilized. Responsive to the identified percentage of available memory currently being utilized, physical memory is dynamically reallocated.

Abstract: A memory controller and methods implement minimized latency and maximized reliability when data traverses multiple buses. The memory controller includes a dynamic random access memory (DRAM) error correcting code (ECC) checking and correcting circuit and a high speed bus (HSB) ECC checking and correcting circuit. In a first mode for implementing minimized latency, read data is applied directly to the DRAM ECC checking and correcting circuit, bypassing the HSB ECC checking and correcting circuit. In a second mode for implementing maximized reliability, the read data is applied through the HSB ECC checking and correcting circuit to the DRAM ECC checking and correcting circuit.

Abstract: A memory controller performs a mirror copy function in a way that allows processor accesses to memory to continue during the mirror copy operations that make up the mirror copy function. Data integrity of mirror copy operations is assured by protocols set up in the memory controller. The result is a memory controller that performs a mirror copy function in a way that allows normal processor accesses to memory to be interleaved with mirror copy operations, thereby minimizing the impact on system performance of executing the mirror copy function.

Abstract: Systems and methods to respond to error detection are provided. A particular method may include issuing a first command to a first redrive device and a second command to a second redrive device. The method may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method may further include storing at a first buffer first data that is received from the first redrive device in response to the first command. The method may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also may include merging the second data with the first data.

Abstract: Systems and methods to respond to schedule commands at a memory controller are disclosed. A transmission error between a first memory controller port and a first redrive device may be detected. A first corrective action may be initiated at the first memory controller port in response to the detection of the transmission error. A particular method may include determining that a second memory controller port initiated a second corrective action. Incoming read commands may be distributed based on a comparison of the first corrective action and the second corrective action.

Abstract: Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port.

Abstract: A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of relatively light memory workload versus a period of relatively heavy workload. The memory controller provides a relatively higher priority for scrub requests near an end of a scrub period if scrub progress is behind an expected scrub progress.

Abstract: A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller includes a scrub controller configured to output more than one scrub request during a particular request selector cycle. The memory controller includes a request selector that services a read request, a write request, or one of the scrub requests during a request selector cycle.

Abstract: In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected.

Abstract: The present invention describes improving the scheduling of read commands on a mirrored memory computer system by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.

Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

Abstract: In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending an first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.

Abstract: A memory controller and a method for improved computer system performance invalidates (i.e., cancels or does not allow for execution of) speculative or unnecessary scrub write commands as part of the periodic execution of the overall scrub command upon the occurrence of certain events, such as if the error checking and correction (ECC) operation indicates that the data were received without error or if the ECC operation indicates that the data received have an uncorrectable error.

Abstract: In a system for communicating data from a processor to a plurality of register groupings that includes a plurality of registers and a plurality of register decoding logic entities, each register is associated with one of the plurality of register groupings. The plurality of register decoding logic entities is arranged in a data communication ring and is assigned to a register grouping.

Abstract: The present invention is generally directed to a method, system, and program product wherein at least two memory ports associated within a memory controller are capable of transferring commands between one another in unbalanced memory configurations. When the first memory port can no longer accept commands and a second memory port is able to accept commands, the second memory port accepts the commands that the first memory port can not. When the first memory port is able to accept commands, and there are commands in the second memory port that should have been in the first memory port, the commands in the second memory port are transferred to the first memory port.

Abstract: The present invention is generally directed to a method, system, and program product wherein at least one command in a first queue is transferred to a second queue. When the first queue can no longer accept command(s) and a second queue is able to accept command(s), the second queue accepts the command(s) that the first queue can not. When the first queue is able to accept command(s), and there are command(s) in the second memory port that should have been in the first queue, the command(s) in the second queue are transferred to the first queue.

Abstract: A method and apparatus to maintain memory read error information concurrently across multiple ranks in a computer memory. An error detection unit associates a read error with a particular rank and with a particular chip in the rank. The error detection unit reports the error and the associated rank ID and chip ID to an error logging unit. The error logging unit maintains, for each rank ID and chip ID for which an error has been detected, a total number of errors that occur. A memory controller uses a fault pattern in the error logging unit to replace failing memory chips or memory ranks with a spare memory chip or a spare memory rank.

Abstract: In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected.

Abstract: A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit atomic read-correct-write operation. The result is a memory controller that efficiently scrubs memory while minimizing the impact of scrub cycles on system performance.