Patents by Inventor Ellie Y. Yieh

Ellie Y. Yieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for fabricating nanowire for semiconductor applications
    Patent number: 10269571
    Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, maintaining a process pressure at greater than 5 bar, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 23, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Keith Tatseun Wong, Shiyu Sun, Sean S. Kang, Nam Sung Kim, Srinivas D. Nemani, Ellie Y. Yieh
  • SELECTIVE DEPOSITION OF METAL SILICIDES
    Publication number: 20190103278
    Abstract: Embodiments of the disclosure relate to selective metal silicide deposition methods. In one embodiment, a substrate having a silicon containing surface is heated and the silicon containing surface is hydrogen terminated. The substrate is exposed to sequential cycles of a MoF6 precursor and a Si2H6 precursor which is followed by an additional Si2H6 overdose exposure to selectively deposit a MoSix material comprising MoSi2 on the silicon containing surface of the substrate. Methods described herein also provide for selective native oxide removal which enables removal of native oxide material without etching bulk oxide materials.
    Type: Application
    Filed: November 13, 2018
    Publication date: April 4, 2019
    Inventors: Raymond HUNG, Namsung KIM, Srinivas D. NEMANI, Ellie Y. YIEH, Jong CHOI, Christopher AHLES, Andrew KUMMEL
  • Gas control in process chamber
    Patent number: 10240232
    Abstract: A process chamber is provided including a sidewall, a substrate support, and an exhaust vent disposed above the substrate support. A processing region is formed between the exhaust vent and substrate support, and the exhaust vent is coupled to an exhaust device configured to create a low pressure at the exhaust vent relative to the processing region. The process chamber further includes a gas ring including an annular shaped body having an inner surface that circumscribes an annular region. The gas ring further includes a plurality of first nozzles that are coupled to a first gas source and configured to deliver a first gas to the processing region. The gas ring further includes a plurality of second nozzles that are coupled to a second gas source and configured to deliver a second gas to the processing region.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: March 26, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Qiwei Liang, Srinivas D. Nemani, Ellie Y. Yieh
  • SEAM-HEALING METHOD UPON SUPRA-ATMOSPHERIC PROCESS IN DIFFUSION PROMOTING AMBIENT
    Publication number: 20190051557
    Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 14, 2019
    Inventors: Bencherki MEBARKI, Sean S. KANG, Keith Tatseun WONG, He REN, Mehul B. NAIK, Ellie Y. YIEH, Srinivas D. NEMANI
  • METHODS FOR FABRICATING NANOWIRE FOR SEMICONDUCTOR APPLICATIONS
    Publication number: 20190019681
    Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, maintaining a process pressure at greater than 5 bar, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.
    Type: Application
    Filed: July 12, 2017
    Publication date: January 17, 2019
    Inventors: Keith Tatseun WONG, Shiyu SUN, Sean S. KANG, Nam Sung KIM, Srinivas D. NEMANI, Ellie Y. YIEH
  • Silicon Nitride Films With High Nitrogen Content
    Publication number: 20190013197
    Abstract: Methods for depositing silicon nitride films with higher nitrogen content are described. Certain methods comprise exposing a substrate to a silicon-nitrogen precursor and ammonia plasma to form a flowable polymer, and then curing the polymer to form a silicon nitride film. Certain methods cure the flowable polymer without the use of a UV-cure process. Also described is the film generated by the methods described above.
    Type: Application
    Filed: July 5, 2018
    Publication date: January 10, 2019
    Inventors: Atashi Basu, Srinivas D. Nemani, Ellie Y. Yieh
  • Methods and apparatus for transferring a substrate
    Patent number: 10153187
    Abstract: Embodiments method and apparatus for transferring a substrate are provided herein. In some embodiments, a substrate cassette includes a body having an upper portion and a lower portion, the upper portion and the lower portion defining an interior volume when the upper portion is coupled to the lower portion; a locking mechanism moveable between a locked position, in which the upper and lower portions are coupled, and an unlocked position, in which the lower portion can be separated from the upper portion; and a load distribution plate coupled to an upper surface of the upper portion along an edge of the upper portion to distribute a load applied to the load distribution plate.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: December 11, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sriskantharajah Thirunavukarasu, Eng Sheng Peh, Srinivas D. Nemani, Arvind Sundarrajan, Avinash Avula, Ellie Y. Yieh
  • HIGH PRESSURE TREATMENT OF SILICON NITRIDE FILM
    Publication number: 20180342384
    Abstract: Methods and systems relating to processes for treating a silicon nitride film on a workpiece including supporting the workpiece in a chamber, introducing an amine gas into the chamber and establishing a pressure of at least 5 atmospheres, and exposing the silicon nitride film on the workpiece to the amine gas while the pressure in the chamber is at least 5 atmospheres.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: Keith Tatseun Wong, Sean Kang, Srinivas D. Nemani, Ellie Y. Yieh
  • TUNGSTEN DEFLUORINATION BY HIGH PRESSURE TREATMENT
    Publication number: 20180342396
    Abstract: Methods and systems relating to processes for treating a tungsten film on a workpiece including supporting the workpiece in a chamber, introducing hydrogen gas into the chamber and establishing a pressure of at least 5 atmospheres, and exposing the tungsten film on the workpiece to the hydrogen gas while the pressure in the chamber is at least 5 atmospheres.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: Keith Tatseun Wong, Thomas Jongwan Kwon, Sean Kang, Ellie Y. Yieh
  • Methods for forming fin structures with desired profile for 3D structure semiconductor applications
    Patent number: 10128337
    Abstract: Methods for forming fin structures with desired profile and dimensions for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. The methods include a structure reshaping process to reshape a shaped structure, such as a diamond like structure formed on a fin structure. In one embodiment, a method for forming a structure on a substrate includes performing an epitaxial deposition process to form a shaped structure on a fin structure disposed on a substrate, performing a mask layer deposition process to form a mask layer having a first width on the shaped structure, and performing a mask trimming process to trim the mask layer from the first width from a second width.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 13, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Jie Zhou, Zhong Qiang Hua, Chentsau Ying, Srinivas D. Nemani, Ellie Y. Yieh
  • Gapfill film modification for advanced CMP and recess flow
    Patent number: 10096512
    Abstract: Implementations described herein relate to methods for forming gap fill materials. After the gap fill material is deposited and before a CMP process is performed on the gap fill material, one or more ion implantation processes are utilized to treat the deposited gap fill material. The one or more ion implantation processes include implanting a first ion species in the gap fill material using a first ion energy, and then implanting a second ion species in the gap fill material using a second ion energy that's lower than the first ion energy. The one or more ion implantation processes minimize CMP dishing and improve recess profile.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Erica Chen, Ludovic Godet, Srinivas D. Nemani, Ellie Y. Yieh
  • Seam-healing method upon supra-atmospheric process in diffusion promoting ambient
    Patent number: 10049927
    Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 14, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Sean Kang, Keith Tatseun Wong, He Ren, Mehul B. Naik, Ellie Y. Yieh, Srinivas D. Nemani
  • METHOD TO IMPROVE FILM QUALITY FOR PVD CARBON WITH REACTIVE GAS AND BIAS POWER
    Publication number: 20180209037
    Abstract: Embodiments of the present disclosure generally describe methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, using a high power impulse magnetron sputtering (HiPIMS) process, and in particular, biasing of the substrate during the deposition process and flowing a nitrogen source gas and/or a hydrogen source gas into the processing chamber in addition to an inert gas to improve the morphology and film stress of the deposited amorphous carbon layer.
    Type: Application
    Filed: November 22, 2017
    Publication date: July 26, 2018
    Inventors: Bhargav CITLA, Jingjing LIU, Zhong Qiang HUA, Chentsau YING, Srinivas D. NEMANI, Ellie Y. YIEH
  • HYBRID LASER AND IMPLANT TREATMENT FOR OVERLAY ERROR CORRECTION
    Publication number: 20180136569
    Abstract: Embodiments disclosed herein relate to methods and systems for correcting overlay errors on a surface of a substrate. A processor performs a measurement process on a substrate to obtain an overlay error map. The processor determines an order of treatment for the substrate based on the overlay error map. The order of treatment includes one or more treatment processes. The processor generates a process recipe for a treatment process of the one or more treatment processes in the order of treatment. The processor provides the process recipe to a substrate treatment apparatus.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 17, 2018
    Inventors: Mangesh BANGAR, Srinivas D. NEMANI, Steve G. GHANAYEM, Ellie Y. YIEH
  • STRESS BALANCED ELECTROSTATIC SUBSTRATE CARRIER WITH CONTACTS
    Publication number: 20180122679
    Abstract: A substrate carrier with contacts is described that is balanced for thermal stress. In one example workpiece carrier has a rigid substrate configured to support a workpiece to be carried for processing, a first dielectric layer over the substrate, an electrostatic conductive electrode over the first dielectric layer to electrostatically hold the workpiece to be carried, a second dielectric layer over the electrode to electrically isolate the workpiece from the electrode, and a third dielectric layer under the substrate to counter thermal stress applied to the substrate by the first and second dielectric layers.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 3, 2018
    Inventors: Shambhu N. Roy, Gautam Pisharody, Seshadri Ramaswami, Srinivas D. Nemani, Zhong Qiang Hua, Douglas A. Buchberger, JR., Niranjan Kumar, Ellie Y. Yieh
  • Selective atomic layer deposition process utilizing patterned self assembled monolayers for 3D structure semiconductor applications
    Patent number: 9911594
    Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Ellie Y. Yieh, Ludovic Godet, Yin Fan
  • PROCESSED WAFER AS TOP PLATE OF A WORKPIECE CARRIER IN SEMICONDUCTOR AND MECHANICAL PROCESSING
    Publication number: 20180025931
    Abstract: A processed wafer is described that may be used as a workpiece carrier in semiconductor and mechanical processing. In some examples, the workpiece carrier includes a substrate, an electrode formed on the substrate to carry an electric charge to grip a workpiece, a through hole through the substrate and connected to the electrode, and a dielectric layer over the substrate to isolate the electrode from the workpiece.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 25, 2018
    Inventors: Srinivas D. Nemani, Shambhu N. Roy, Gautam Pisharody, Douglas A. Buchberger, JR., Ellie Y. Yieh, Zhong Qiang Hua
  • Silicide phase control by confinement
    Patent number: 9865466
    Abstract: Implementations described herein generally relate to methods of selective deposition of metal silicides. More specifically, implementations described herein generally relate to methods of forming nickel silicide nanowires for semiconductor applications. In one implementation, a method of processing a substrate is provided. The method comprises forming a silicon-containing layer on a surface of a substrate, forming a metal-containing layer comprising a transition metal on the silicon-containing layer, forming a confinement layer on exposed surfaces of the metal-containing layer and annealing the substrate at a temperature of less than 400 degrees Celsius to form a metal silicide layer from the silicon-containing layer and the metal-containing layer, wherein the confinement layer inhibits formation of metal-rich metal silicide phases.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 9, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Ellie Y. Yieh, Mehul B. Naik, Srinivas D. Nemani
  • Single platform, multiple cycle spacer deposition and etch
    Patent number: 9852916
    Abstract: A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 26, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Hao Chen, Chentsau (Chris) Ying, Srinivas D. Nemani, Ellie Y. Yieh
  • SEAM-HEALING METHOD UPON SUPRA-ATMOSPHERIC PROCESS IN DIFFUSION PROMOTING AMBIENT
    Publication number: 20170358490
    Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.
    Type: Application
    Filed: October 24, 2016
    Publication date: December 14, 2017
    Inventors: Bencherki MEBARKI, Sean KANG, Keith Tatseun WONG, He REN, Mehul B. NAIK, Ellie Y. YIEH, Srinivas D. NEMANI