Patents by Inventor Elona Erez
Elona Erez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230157675Abstract: A system to retrieve medical X-rays includes a trained convolutional neural network (CNN), a balancing feature generator, a balancing type selector, and a K-Nearest Neighbor (KNN) classifier. The trained CNN encodes a plurality of diagnosed X-ray images into a plurality of candidate embeddings, and encodes a partially diagnosed X-ray image into a query embedding. The balancing feature generator produces a plurality of virtual candidate embeddings from the query embedding and the plurality of candidate embeddings. The balancing type selector selects a subset of the plurality of virtual candidate embeddings. The KNN classifier performs a KNN search between the query embedding and a plurality of the candidate embeddings and the subset of the plurality of virtual candidate embeddings.Type: ApplicationFiled: September 5, 2022Publication date: May 25, 2023Inventors: Elona EREZ, Avidan AKERIB
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Publication number: 20220384039Abstract: A system for cancer type prediction includes a trained neural network (NN), a patient feature-set extractor (PFE), and an associative feature-set searcher (FSS). The trained NN receives a patient input vector from a patient record and generates cancer type predictions. The PFE extracts a known cancer feature set from patient input vector from a patient record with a known cancer type, and an unknown cancer feature set from a patient input vector from a patient record without a known cancer type, when passed through the trained NN. The FSS stores a known cancer feature set in a first portion of a column, and metadata in a second portion of a column, and finds K nearest neighbors of the unknown cancer feature set from among the stored known cancer feature sets.Type: ApplicationFiled: April 28, 2022Publication date: December 1, 2022Inventor: Elona EREZ
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Publication number: 20220108772Abstract: A protein searcher includes a pre-trained CNN, a feature extractor, a database and a KNN searcher. The pre-trained CNN, trained on a previously classified amino acid database, receives an unidentified amino acid sequence. The feature extractor extracts a feature vector of the unidentified amino acid sequence as a query feature vector. The database stores feature vectors of trained amino acid sequences and of at least one untrained amino acid sequence and stores associated classes of the trained amino acid sequences and associated tags of the at least one untrained amino acid sequence. The KNN searcher finds K feature vectors of the database which are close to the query feature vector and outputs the associated class or tag of each of the K feature vectors.Type: ApplicationFiled: September 30, 2021Publication date: April 7, 2022Inventor: Elona EREZ
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Publication number: 20210334582Abstract: A system for detecting changes between two temporally different images includes an image divider, a Convolutional Neural Network (CNN) feature encoder, an image alignment system, a feature comparator, a CNN feature decoder and segmenter, and a block combiner. The image divider divides a first and second image into a plurality of image blocks. CNN feature encoder encodes the image blocks from the first and second image into first and second feature sets respectively. The image alignment system aligns the first and second image by searching for matching anchor vectors in the first and second feature sets using a similarity search. The feature comparator produces change feature sets from the first and second feature sets of the aligned image blocks, and the CNN feature decoder and segmenter creates segmented change image blocks from the change feature sets. The block combiner combines segmented change image blocks into a segmented change image.Type: ApplicationFiled: April 12, 2021Publication date: October 28, 2021Inventors: Elona EREZ, Avidan AKERIB
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Publication number: 20210287762Abstract: A system for finding similar molecules to a query molecule includes a GCN, a PFS vector extractor, a compensated vector comparator (CVC) and a candidate vector selector. The GCN has been trained to output a molecular property vector from an input query or input candidate molecular vectors, respectively, The GCN transforms query atomic feature set (AFS) vectors and candidate AFS vectors into query property feature set (PFS) embedding vectors and candidate PFS embedding vectors. The PFS vector extractor extracts query PFS embedding vectors and candidate PFS embedding vectors from hidden layers of the trained GCN. The compensated vector comparator (CVC) calculates a compensated similarity metric (CSM) for at least one pair of query PFS embedding vector and one candidate PFS embedding vector. The candidate vector selector selects only such candidate molecular vectors.Type: ApplicationFiled: March 14, 2021Publication date: September 16, 2021Inventor: Elona EREZ
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Publication number: 20210056085Abstract: A deduplication system includes a similarity searcher, a difference calculator, and a storage manager. The similarity searcher searches for a similar fingerprint in a database storing a plurality of local sensitive fingerprints, resembling a new fingerprint of a new block. The difference calculator computes a difference block between the input block and a similar block associated with the found similar fingerprint, and the storage manager updates the database with the new fingerprint and stores the difference block, if not empty, in a store. A method for deduplication includes searching in a database, storing a plurality of local sensitive fingerprints, a similar fingerprint, resembling a new fingerprint of a new block, calculating a difference block between the input block and a similar block associated with the similar fingerprint, if found, updating the database with the new fingerprint and storing the difference block, if it is not empty, in a storage unit.Type: ApplicationFiled: June 25, 2020Publication date: February 25, 2021Inventors: Avidan AKERIB, Dan ILAN, Eli EHRMAN, Elona EREZ
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Patent number: 10606760Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.Type: GrantFiled: August 23, 2017Date of Patent: March 31, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Elona Erez, Avner Dor, Moshe Twitto, Jun Jin Kong
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Patent number: 10528466Abstract: A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.Type: GrantFiled: June 7, 2018Date of Patent: January 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Won Lee, Dashevsky Shmuel, Moshe Twitto, Elona Erez, Eran Hof, Jun-Jin Kong, Avner Dor, Michael Erlihson
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Publication number: 20190266482Abstract: A method for a neural network includes concurrently calculating a distance vector between an output feature vector describing an unclassified item and each of a plurality of qualified feature vectors, each describing one classified item out of a collection of classified items. The method includes concurrently computing a similarity score for each distance vector and creating a similarity score vector of the plurality of computed similarity scores. A system for a neural network includes an associative memory array, an input arranger, a hidden layer computer and an output handler. The input arranger manipulates information describing an unclassified item stored in the memory array. The hidden layer computer computes a hidden layer vector. The output handler computes an output feature vector and concurrently calculates a distance vector between an output feature vector and each of a plurality of qualified feature vectors, and concurrently computes a similarity score for each distance vector.Type: ApplicationFiled: February 26, 2018Publication date: August 29, 2019Inventor: Elona Erez
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Patent number: 10387254Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n?{tilde over (k)}j, where the first n-kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix R, of dimension (n?{tilde over (k)}j)(n?{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n?kl columns Tj and has k1?{tilde over (k)}j columns; finding a vector c?(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n?{tilde over (k)}j; and solving ( A | I ) ? ( a b ) = ( Q j | T j ) ? s ~ = T j ? s ? ? where ? ? a = 0 ?Type: GrantFiled: October 12, 2017Date of Patent: August 20, 2019Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Moshe Twitto, Yaron Shany, Avner Dor, Elona Erez, Jun Jin Kong
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Patent number: 10333554Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises ?t syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of ?t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n?1; and multiplying s by a right submatrix ? of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=?·s.Type: GrantFiled: June 30, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moshe Twitto, Moshe Ben Ari, Avner Dor, Elona Erez, Jun Jin Kong, Yaron Shany
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Patent number: 10289561Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.Type: GrantFiled: August 8, 2017Date of Patent: May 14, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Elona Erez, Avner Dor, Jun-Jin Kong
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Publication number: 20190114228Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity Matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n?{tilde over (k)}j, where the first n?kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix Rj of dimension (n?{tilde over (k)}j)(n?{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n?kl columns and Tj has k1?{tilde over (k)} columns; finding a vector c=(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n?{tilde over (k)}j; and solving ( A | I ) ? ( a b ) = ( Q j | T j ) ? s ~ = T j ? s where a=0 and b=Tjs, and codType: ApplicationFiled: October 12, 2017Publication date: April 18, 2019Inventors: MOSHE TWITTO, YARON SHANY, AVNER DOR, ELONA EREZ, JUN JIN KONG
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Patent number: 10262728Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.Type: GrantFiled: October 7, 2016Date of Patent: April 16, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Iddo Naiss, Noam Livne, Elona Erez, Jun Jin Kong
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Publication number: 20190065392Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.Type: ApplicationFiled: August 23, 2017Publication date: February 28, 2019Inventors: Elona EREZ, Avner DOR, Moshe TWITTO, Jun Jin KONG
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Publication number: 20190050343Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.Type: ApplicationFiled: August 8, 2017Publication date: February 14, 2019Inventors: ELONA EREZ, AVNER DOR, JUN-JIN KONG
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Patent number: 10198203Abstract: A memory system includes a table storing a plurality of entries, where each entry is associated with a different logical block address (LBA), a plurality of memory devices, channels, and ways, where each memory device is connected to one of the channels ways and to one of the ways, and a memory controller configured to receive an LBA and data from a host, execute a plurality of pseudo-random functions on the received LBA to generate a plurality of slot indexes, select one of the slot indexes, write the data to one of the memory devices identified by the selected one slot index, and update a corresponding one of the entries to include the selected one slot index.Type: GrantFiled: November 15, 2016Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Michael Erlihson, Shmuel Dashevsky, Elona Erez, Guy Inbar, Jun Jin Kong, Keon Soo Ha
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Publication number: 20190007062Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises ?t syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of ?t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n?1; and multiplying s by a right submatrix ? of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=?·s.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: MOSHE TWITTO, MOSHE BEN ARI, AVNER DOR, ELONA EREZ, JUN JIN KONG, YARON SHANY
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Publication number: 20180357164Abstract: A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Inventors: Jong-Won Lee, Dashevsky Shmuel, Moshe Twitto, Elona Erez, Eran Hof, Jun-Jin Kong, Avner Dor, Michael Erlihson
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Publication number: 20180136865Abstract: A memory system includes a table storing a plurality of entries, where each entry is associated with a different logical block address (LBA), a plurality of memory devices, channels, and ways, where each memory device is connected to one of the channels ways and to one of the ways, and a memory controller configured to receive an LBA and data from a host, execute a plurality of pseudo-random functions on the received LBA to generate a plurality of slot indexes, select one of the slot indexes, write the data to one of the memory devices identified by the selected one slot index, and update a corresponding one of the entries to include the selected one slot index.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Inventors: MICHAEL ERLIHSON, SHMUEL DASHEVSKY, ELONA EREZ, GUY INBAR, JUN JIN KONG, KEON SOO HA