Abstract: Systems and methods for measuring the effective thermal conductivity of aggregate packed beds are described. Systems and methods may include an apparatus comprising a first assembly, a second assembly, and a cylindrical insulator. The first assembly may include a first faucet, a first brass cover, a first heat exchanger body, and a first aluminum plate. The second assembly may include a second faucet, a second brass cover, a second heat exchanger body, and a second aluminum plate. The first assembly and the second assembly may be placed into opposite ends of the cylindrical insulator. Aggregates may be placed inside the cylindrical insulator between the first and second assemblies. Temperature may be measured at a variety of points of contact on the two faces of a low thermal conductivity plate, and heat flux and effective thermal conductivity of packed bed of aggregates may be calculated.

Abstract: Systems and methods for cooling aggregate are described. Systems and methods may include a drum. The drum may include an aggregate inlet; a plurality of buckets arranged in a ring around a circumference of the drum, and a plurality of rings arranged along the length of the drum, wherein each of the plurality of buckets has openings that open into the interior of the drum; one or more radial donuts or radial webs within the interior of the drum; an aggregate outlet; and a cooling air supply.

Abstract: Embodiments of transceivers with one or more reconfigurable antennas are described. In one embodiment, a reconfigurable antenna transceiver includes a transmit chain, a receive chain, and a reconfigurable antenna having a plurality of reconfigurable modes. The transceiver may also include an antenna controller configured to set a mode of the reconfigurable antenna. According to other aspects, the transceiver may also include a signal processor configured to transmit a set of training symbols during a training interval. The antenna controller may be further configured to select a respective mode of the reconfigurable antenna for each training symbol in the set of training symbols. Additionally, the antenna controller may be configured to calculate a received Signal-of-Interest to Interferer Ratio (SIR) for each training symbol of the set of training symbols. In this context, a system utilizing a reconfigurable antenna may achieve significant rate improvement compared to half-duplex systems.

Abstract: Embodiments of full-duplex self-interference cancellation systems are described. In one embodiment, a full-duplex transceiver includes a digital signal processor that processes digital signals, a transmit chain that receives a first digital baseband signal from the digital signal processor and converts it to a first RF signal, a receive chain that receives a second RF signal and converts the second RF signal to a second digital baseband signal, and an auxiliary receive chain that receives a portion of the first RF signal and converts it to an auxiliary digital baseband signal. The transceiver may further include a self-interference canceller that applies a channel transfer function to the auxiliary digital baseband signal to generate a cancellation signal and subtracts the cancellation signal from the second digital baseband signal to cancel self-interference at the transceiver.

Abstract: Embodiments of full-duplex systems with reconfigurable antennas are described. In one embodiment, a full-duplex reconfigurable antenna transceiver includes a transmit chain, a receive chain, and a reconfigurable antenna having a plurality of reconfigurable modes. The transceiver may also include an antenna controller configured to set a mode of the reconfigurable antenna. According to other aspects, the transceiver may also include a signal processor configured to transmit a set of training symbols during a training interval. The antenna controller may be further configured to select a respective mode of the reconfigurable antenna for each training symbol in the set of training symbols. Additionally, the antenna controller may be configured to calculate a received Signal-of-Interest to Interferer Ratio (SIR) for each training symbol of the set of training symbols. In this context, a full-duplex system utilizing a reconfigurable antenna may achieve significant rate improvement compared to half-duplex systems.

Abstract: Embodiments of full-duplex self-interference cancellation systems are described. In one embodiment, a full-duplex transceiver includes a digital signal processor that processes digital signals, a transmit chain that receives a first digital baseband signal from the digital signal processor and converts it to a first RF signal, a receive chain that receives a second RF signal and converts the second RF signal to a second digital baseband signal, and an auxiliary receive chain that receives a portion of the first RF signal and converts it to an auxiliary digital baseband signal. The transceiver may further include a self-interference canceller that applies a channel transfer function to the auxiliary digital baseband signal to generate a cancellation signal and subtracts the cancellation signal from the second digital baseband signal to cancel self-interference at the transceiver.

Abstract: Systems and methods for cooling aggregate are described. Systems and methods may include a drum. The drum may include an aggregate inlet; a plurality of buckets arranged in a ring around a circumference of the drum, and a plurality of rings arranged along the length of the drum, wherein each of the plurality of buckets has openings that open into the interior of the drum; one or more radial donuts or radial webs within the interior of the drum; an aggregate outlet; and a cooling air supply.

Abstract: Embodiments of full-duplex systems with reconfigurable antennas are described. In one embodiment, a full-duplex reconfigurable antenna transceiver includes a transmit chain, a receive chain, and a reconfigurable antenna having a plurality of reconfigurable modes. The transceiver may also include an antenna controller configured to set a mode of the reconfigurable antenna. According to other aspects, the transceiver may also include a signal processor configured to transmit a set of training symbols during a training interval. The antenna controller may be further configured to select a respective mode of the reconfigurable antenna for each training symbol in the set of training symbols. Additionally, the antenna controller may be configured to calculate a received Signal-of-Interest to Interferer Ratio (SIR) for each training symbol of the set of training symbols. In this context, a full-duplex system utilizing a reconfigurable antenna may achieve significant rate improvement compared to half-duplex systems.

Abstract: Embodiments of full-duplex self-interference cancellation systems are described. In one embodiment, a full-duplex transceiver includes a digital signal processor that processes digital signals, a transmit chain that receives a first digital baseband signal from the digital signal processor and converts it to a first RF signal, a receive chain that receives a second RF signal and converts the second RF signal to a second digital baseband signal, and an auxiliary receive chain that receives a portion of the first RF signal and converts it to an auxiliary digital baseband signal. The transceiver may further include a self-interference canceller that applies a channel transfer function to the auxiliary digital baseband signal to generate a cancellation signal and subtracts the cancellation signal from the second digital baseband signal to cancel self-interference at the transceiver.

Abstract: One embodiment provides a method of performing packet identifier (PID) filtering of a digital video broadcasting-handheld (DVB-H) transport stream and includes processing a PID and a continuity counter (CC) sequence of the DVB-H transport stream, computing a number of mismatched bits between the PID and a desired PID, proceeding to a start of a reset state on a first-in-first-out (FIFO) queue of the DVB-H transport stream when a FIFO buffer becomes full, determining if a number of mismatched bits of a first packet in the FIFO buffer is less than a first threshold value, and proceeding to a start of a run algorithm state only if the number of mismatched bits of the first packet in the FIFO buffer is less than the first threshold value and if there is a valid CC sequence that includes the first packet.

Abstract: A method of estimating a coarse frequency offset of Digital Multimedia Broadcasting (DMB) transmission frames includes receiving the DMB transmission frames including a synchronization channel having a phase reference symbol, circularly shifting the phase reference symbol by applying a circular shift to the phase reference symbol, numerically correlating the circularly shifted phase reference symbol with a known correct phase reference symbol to obtain a highest peak and a side peaks of the numeric correlation, and computing a phase reference symbol angle based on a multiplication of the peak and a carrier spacing of the DMB transmission frames. The peak is determined when the circularly shifted phase reference symbol is equal to the known correct phase reference symbol. The peak and side peaks corresponding to the peak are operated in a range of a maximum value of the circular shift.

Abstract: FEC frame synchronization in a DAB-IP system comprising FEC frames includes receiving FEC packets each comprising a FEC packet header and a FEC data field comprising padding bytes at an end of a last FEC packet received; comparing a received FEC packet header with a known FEC packet header until a number of bit errors in the received FEC packet header is less than or equal to a predetermined amount; and matching the received FEC packet header and the padding bytes until at least one of the following actions occur thereby resulting in receiver locking: a number of successive FEC packet headers mismatches in the received FEC packet header; a predetermined number of FEC packets end without padding matching; and FEC packet header and padding matching occurs. The received FEC packets are tracked after receiver locking has occurred to ensure FEC parity packets are positioned properly in the FEC frames.

Abstract: A method of estimating a coarse frequency offset of Digital Multimedia Broadcasting (DMB) transmission frames includes receiving the DMB transmission frames including a synchronization channel having a phase reference symbol, circularly shifting the phase reference symbol by applying a circular shift to the phase reference symbol, numerically correlating the circularly shifted phase reference symbol with a known correct phase reference symbol to obtain a highest peak and a side peaks of the numeric correlation, and computing a phase reference symbol angle based on a multiplication of the peak and a carrier spacing of the DMB transmission frames. The peak is determined when the circularly shifted phase reference symbol is equal to the known correct phase reference symbol. The peak and side peaks corresponding to the peak are operated in a range of a maximum value of the circular shift.

Abstract: One embodiment provides a method of performing packet identifier (PID) filtering of a digital video broadcasting-handheld (DVB-H) transport stream and includes processing a PID and a continuity counter (CC) sequence of the DVB-H transport stream, computing a number of mismatched bits between the PID and a desired PID, proceeding to a start of a reset state on a first-in-first-out (FIFO) queue of the DVB-H transport stream when a FIFO buffer becomes full, determining if a number of mismatched bits of a first packet in the FIFO buffer is less than a first threshold value, and proceeding to a start of a run algorithm state only if the number of mismatched bits of the first packet in the FIFO buffer is less than the first threshold value and if there is a valid CC sequence that includes the first packet.

Abstract: FEC frame synchronization in a DAB-IP system comprising FEC frames includes receiving FEC packets each comprising a FEC packet header and a FEC data field comprising padding bytes at an end of a last FEC packet received; comparing a received FEC packet header with a known FEC packet header until a number of bit errors in the received FEC packet header is less than or equal to a predetermined amount; and matching the received FEC packet header and the padding bytes until at least one of the following actions occur thereby resulting in receiver locking: a number of successive FEC packet headers mismatches in the received FEC packet header; a predetermined number of FEC packets end without padding matching; and FEC packet header and padding matching occurs. The received FEC packets are tracked after receiver locking has occurred to ensure FEC parity packets are positioned properly in the FEC frames.