Abstract: The problem of a potentially high amount of supra-threshold charge passing through the patient's tissue at the end of an Implantable Pulse Generator (IPG) program is addressed by circuitry that periodically dissipates only small amount of the charge stored on capacitances (e.g., DC-blocking capacitors) during a pulsed post-program recovery period. This occurs by periodically activating control signals to turn on passive recovery switches to form a series of discharge pulses each dissipating a sub-threshold amount of charge. Such periodic pulsed dissipation may extend the duration of post-program recovery, but is not likely to be noticeable by the patient when the programming in the IPG changes from a first to a second program. Periodic pulsed dissipation of charge may also be used during a program, such as between stimulation pulses.

Abstract: The problem of a potentially high amount of supra-threshold charge passing through the patient's tissue at the end of an Implantable Pulse Generator (IPG) program is addressed by circuitry that periodically dissipates only small amount of the charge stored on capacitances (e.g., DC-blocking capacitors) during a pulsed post-program recovery period. This occurs by periodically activating control signals to turn on passive recovery switches to form a series of discharge pulses each dissipating a sub-threshold amount of charge. Such periodic pulsed dissipation may extend the duration of post-program recovery, but is not likely to be noticeable by the patient when the programming in the IPG changes from a first to a second program. Periodic pulsed dissipation of charge may also be used during a program, such as between stimulation pulses.

Abstract: An electrical stimulation system includes at least one electrical stimulation lead having stimulation electrodes; and a processor coupled to the at least one electrical stimulation lead to perform actions, including: directing delivery of at least one stimulation pulse to tissue of a patient during each charge injection phase, where each consecutive pair of the charge injection phases is separated by a charge recovery phase; and, for at least one stimulation pulse: during delivery of the stimulation pulse, directing application of at least one charge recovery pulse to interrupt the delivery of the stimulation pulse, where each one of the at least one charge recovery pulse has a relative amplitude that is larger in magnitude than an amplitude of the stimulation pulse; and, after application of the charge recovery pulse, directing resumption of delivery of the stimulation pulse at the amplitude of the stimulation pulse.

Abstract: An implantable medical device, such as an implantable pulse generator, includes a case; an integrated circuit device disposed within the case, the integrated circuit device including a temperature sensor; and a thermal coupling medium disposed between, and in contact with, the case and the integrated circuit device, wherein the thermal coupling medium is a solid, liquid, gel, or any combination thereof.

Abstract: Recovery circuitry for passively recovering charge from capacitances at electrodes in an Implantable Pulse Generator (IPG) is disclosed. The passive recovery circuitry includes passive recovery switches intervening between each electrode node and a common reference voltage, and each switch is in series with a variable resistance that may be selected based on differing use models of the IPG. The passive recovery switches may also be controlled in different modes. For example, in a first mode, the only recovery switches closed after a stimulation pulse are those associated with electrodes used to provide stimulation. In a second mode, all recovery switches are closed after a stimulation pulse, regardless of the electrodes used to provide stimulation. In a third mode, all recovery switches are closed continuously, which can provide protection when the IPG is in certain environments (e.g., MRI), and which can also be used during stimulation therapy itself.

Abstract: A compliance voltage management algorithm is disclosed for managing the compliance voltage, VH, that powers the DAC circuitry in a stimulator device. A user can use a user interface associated with an external programming device to define a time-varying stimulation waveform to be programmed into the stimulator device. The algorithm analyzes the prescribed waveform and determines a number of groups of pulses that will be treated similarly from a VH management standpoint. Optimal compliance voltages are determined for each group, as are the rise and fall rates at which VH is able to change at transitions between groups. These rise or fall rates in VH are then used to set when the compliance voltage should increase or decrease. For example, the algorithm will automatically set VH to start rising in advance of a transition so that it is at the proper higher value when the transition occurs.

Abstract: Techniques for sensing neural responses such as Evoked Compound Action Potentials (ECAPs) in an implantable stimulator device are disclosed. A first therapeutic pulse phase is followed by a charge recovery phase that includes at least one high-impedance passive charge recovery duration. The ECAP is sensed during the high-impedance passive charge recovery duration. The time period of the passive charge recovery is lengthened and the high-impedance passive recharge duration entirely overlaps the ECAP (i.e., the neural response duration) at the sensing electrode.

Abstract: An architecture is disclosed for an Implantable Pulse Generator having improved compliance voltage monitoring and adjustment software and hardware. Software specifies which stimulation pulses are to be measured as relevant to monitoring and adjusting the compliance voltage. Preferably, specifying such pulses occurs by setting a compliance monitoring instruction (e.g., a bit) in the program that defines the pulse, and the compliance monitor bit instruction may be set at a memory location defining a particular pulse phase during which the compliance voltage should be monitored. When a compliance monitor instruction issues, the active electrode node voltages are monitored and compared to desired ranges to determine whether they are high or low. Compliance logic operates on these high/low signals and processes them to decide whether to issue a compliance voltage interrupt to the microcontroller, which can then command the compliance voltage generator to increase or decrease the compliance voltage.

Abstract: Disclosed herein are circuits and methods for a multi-electrode implantable stimulator device incorporating one decoupling capacitor in the current path established via at least one cathode electrode and at least one anode electrode. In one embodiment, the decoupling capacitor may be hard-wired to a dedicated anode on the device. The cathodes are selectively activatable via stimulation switches. In another embodiment, any of the electrodes on the devices can be selectively activatable as an anode or cathode. In this embodiment, the decoupling capacitor is placed into the current path via selectable anode and cathode stimulation switches. Regardless of the implementation, the techniques allow for the benefits of capacitive decoupling without the need to associate decoupling capacitors with every electrode on the multi-electrode device, which saves space in the body of the device.

Abstract: Recovery circuitry for passively recovering charge from capacitances at electrodes in an Implantable Pulse Generator (IPG) is disclosed. The passive recovery circuitry includes passive recovery switches intervening between each electrode node and a common reference voltage, and each switch is in series with a variable resistance that may be selected based on differing use models of the IPG. The passive recovery switches may also be controlled in different modes. For example, in a first mode, the only recovery switches closed after a stimulation pulse are those associated with electrodes used to provide stimulation. In a second mode, all recovery switches are closed after a stimulation pulse, regardless of the electrodes used to provide stimulation. In a third mode, all recovery switches are closed continuously, which can provide protection when the IPG is in certain environments (e.g., MRI), and which can also be used during stimulation therapy itself.

Abstract: An architecture is disclosed for an Implantable Pulse Generator having improved compliance voltage monitoring and adjustment software and hardware. Software specifies which stimulation pulses are to be measured as relevant to monitoring and adjusting the compliance voltage. During compliance voltage monitoring, “high-side” anode electrode node voltages referenced to the compliance voltage are considered as are “low-side” cathode electrode node voltages referenced to ground. Translation stages are used to convert only the anode electrode node voltages to ground as low-side signals. This allows compliance voltage monitoring and adjustment to occur using only low-side signals, which eases sensing and reduces design complexity.

Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: An architecture is disclosed for an Implantable Pulse Generator having improved compliance voltage monitoring and adjustment software and hardware. Software specifies which stimulation pulses are to be measured as relevant to monitoring and adjusting the compliance voltage. Preferably, specifying such pulses occurs by setting a compliance monitoring instruction (e.g., a bit) in the program that defines the pulse, and the compliance monitor bit instruction may be set at a memory location defining a particular pulse phase during which the compliance voltage should be monitored. When a compliance monitor instruction issues, the active electrode node voltages are monitored and compared to desired ranges to determine whether they are high or low. Compliance logic operates on these high/low signals and processes them to decide whether to issue a compliance voltage interrupt to the microcontroller, which can then command the compliance voltage generator to increase or decrease the compliance voltage.

Abstract: A method and system of providing therapy to a patient implanted with an array of electrodes is provided. A train of electrical stimulation pulses is conveyed within a stimulation timing channel between a group of the electrodes to stimulate neural tissue, thereby providing continuous therapy to the patient. Electrical parameter is sensed within a sensing timing channel using at least one of the electrodes, wherein the first stimulation timing channel and sensing timing channel are coordinated, such that the electrical parameter is sensed during the conveyance of the pulse train within time slots that do not temporally overlap any active phase of the stimulation pulses.

Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: The problem of a potentially high amount of supra-threshold charge passing through the patient's tissue at the end of an Implantable Pulse Generator (IPG) program is addressed by circuitry that periodically dissipates only small amount of the charge stored on capacitances (e.g., DC-blocking capacitors) during a pulsed post-program recovery period. This occurs by periodically activating control signals to turn on passive recovery switches to form a series of discharge pulses each dissipating a sub-threshold amount of charge. Such periodic pulsed dissipation may extend the duration of post-program recovery, but is not likely to be noticeable by the patient when the programming in the IPG changes from a first to a second program. Periodic pulsed dissipation of charge may also be used during a program, such as between stimulation pulses.

Abstract: An optical stimulation system includes a light source configured to produce light for optical stimulation; a light monitor; an optical lead coupled, or coupleable, to the light source and the light monitor; and a control module coupled, or coupleable, to the light source and the light monitor. The control module includes a memory, and a processor configured for automatically initiating a verification or measurement of a light output value; receiving, from the light monitor, a measurement of light generated by the light source; and when the measurement deviates from an expected light output value by more than a threshold amount, performing at least one of the following: sending a warning; or taking a corrective action.

Abstract: Recovery circuitry for passively recovering charge from capacitances at electrodes in an Implantable Pulse Generator (IPG) is disclosed. The passive recovery circuitry includes passive recovery switches intervening between each electrode node and a common reference voltage, and each switch is in series with a variable resistance that may be selected based on differing use models of the IPG. The passive recovery switches may also be controlled in different modes. For example, in a first mode, the only recovery switches closed after a stimulation pulse are those associated with electrodes used to provide stimulation. In a second mode, all recovery switches are closed after a stimulation pulse, regardless of the electrodes used to provide stimulation. In a third mode, all recovery switches are closed continuously, which can provide protection when the IPG is in certain environments (e.g., MRI), and which can also be used during stimulation therapy itself.

Abstract: The problem of a potentially high amount of supra-threshold charge passing through the patient's tissue at the end of an Implantable Pulse Generator (IPG) program is addressed by circuitry that periodically dissipates only small amount of the charge stored on capacitances (e.g., DC-blocking capacitors) during a pulsed post-program recovery period. This occurs by periodically activating control signals to turn on passive recovery switches to form a series of discharge pulses each dissipating a sub-threshold amount of charge. Such periodic pulsed dissipation may extend the duration of post-program recovery, but is not likely to be noticeable by the patient when the programming in the IPG changes from a first to a second program. Periodic pulsed dissipation of charge may also be used during a program, such as between stimulation pulses.

Abstract: Digital-to-analog converter (DAC) circuitry for providing currents at electrodes of an Implantable Pulse Generator (IPG) is disclosed. The DAC circuitry includes at least one PDAC for sourcing current to the electrodes, and at least one NDAC for sinking current from the electrodes. The PDACs are powered with power supplies VH (the compliance voltage) and Vssh in a high power domain, and the NDACs are powered with power supplies Vcc and ground in a low power domain. VH may change during IPG operation, and Vssh preferably also changes with a fixed difference with respect to VH. Digital control signals to the PDACs are formed (and possibly converted into) the high power domain, and transistors used to build the PDACs are biased in the high power domain, and thus may also change with VH. This permits transistors in the PDACs and NDACs to be made from normal low-voltage logic transistors.