Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

Abstract: The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The memory array may comprise a plurality of sub-blocks including a first sub-block and a second sub-block. Each sub-block may comprise a memory cell portion of the plurality of memory cells associated with a corresponding word line portion of the plurality of word lines. The memory cell portions in the first and second sub-blocks may be independently addressable with respect to each other such that a second operation can be performed on at least one memory cell of the memory cell portion of the second sub-block responsive to suspending a first operation directed to at least one memory cell of the memory cell portion of the first sub-block.

Abstract: Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described.

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on guard values that correspond to words of the program page. Other embodiments may be described and claimed.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

Abstract: A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when the temperature exceeds a threshold temperature for an amount of time.

Abstract: Example embodiments described herein may relate to memory devices, and may relate more particularly to caching for non-volatile memory devices.

Abstract: Example embodiments described herein may relate to memory devices, and may relate more particularly to configurable address space for non-volatile memory devices.

Abstract: A non-volatile memory device with dynamic allocable regions that are unlocked or locked. Unlocking and/or locking is performed on one region or on multiple regions simultaneously, each region being identified by respective start address and end address. The start and end addresses of a dynamic allocable region need not coincide with physical addresses of a partition.

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

Abstract: Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described.

Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.

Abstract: An e-MMC memory having a controller for a NAND Flash and another controller for a Phase-Change Memory (PCM) in a memory managed system. The different memory technologies of the NAND Flash and PCM may be partitioned to segment available memory space to store different types of data or code while accounting for an attribute property stored in a register.

Abstract: Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

Abstract: A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an external bus interface coupled to an external bus to communicate read and write instructions with an external device, a memory array interface coupled to a memory array to perform reads and writes on a memory array, and an overwrite module to write a desired value to a desired address of the memory array.

Abstract: Subject matter disclosed herein relates to memory devices or accessing memory devices, and more particularly, but by way of example and not limitation, to preparation of a memory device to perform a memory access operation based at least partly on at least one indicator signal that indicates a memory access type.

Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.

Abstract: The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The memory array may comprise a plurality of sub-blocks including a first sub-block and a second sub-block. Each sub-block may comprise a memory cell portion of the plurality of memory cells associated with a corresponding word line portion of the plurality of word lines. The memory cell portions in the first and second sub-blocks may be independently addressable with respect to each other such that a second operation can be performed on at least one memory cell of the memory cell portion of the second sub-block responsive to suspending a first operation directed to at least one memory cell of the memory cell portion of the first sub-block.