Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.

Abstract: A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.

Abstract: A regulator for a digital-to-analog converter having in input a digital signal and suitable for providing an analog signal in output, the regulator including at least one pair of buffers having in input the digital signal and the outputs connected to a pair of circuit branches connected to the output of the regulator; each of the at least two circuit branches having at least one resistance. To at least one of the at least one pair of buffers a variable resistance is associated, and the regulator includes a circuit having in input the analog signal and adapted for measuring its waveform and acting on the variable resistance in response to its possible anomalous waveform compared to a desired waveform.

Abstract: A memory architecture includes a matrix of memory cells structured into rows and columns and associated with a row decoder, an array of reference cells associated with the matrix, a first detector block including plural sense amplifiers associated with the matrix in correspondence with its columns, and a plurality of latch registers connected to the output of the sense amplifiers and interconnected to each other by a references bus which further connects them to a second detector block that includes at least one sense amplifier of the reference cells. The array of reference cells is placed upstream of the wordlines of the matrix taking, as reference, a propagation direction of a voltage signal applied to the memory cells. Moreover, the second detector block includes a stabilized buffer suitable to supply the references bus with an output signal having rise transient stable with respect to working conditions of the architecture.

Abstract: A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.

Abstract: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.

Abstract: A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.

Abstract: A circuit for detecting a logic transition is proposed.

Abstract: A decoding structure for a memory device with a control code is used in a memory including a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel. The decoding structure selectively connects each reading element to a plurality of memory cells, and selectively connects each memory cell to a plurality of reading elements.

Abstract: A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.

Abstract: A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Abstract: A circuit for biasing an input node of a sense amplifier is proposed. The circuit includes a voltage regulator for keeping the input node at a pre-set operative voltage during a sensing operation. The circuit further includes a pulling device for pulling the input node from a starting voltage towards a power supply voltage, the operative voltage being comprised between the starting voltage and the power supply voltage. The circuit also includes a control device for disabling the pulling device before the input node reaches the operative voltage.

Abstract: A sense amplifier structure for multi-level non-volatile memories reads the contents of the memory cells. In particular, a current drawn by a memory cell to be read is compared to a current drawn by a reference cell through a sense amplifier that has one input terminal connected to a circuit node to which said currents are led. Advantageously, the currents are compared at both inputs of the sense amplifier by connecting a second input of said amplifier to a circuit node to which said currents are led, with opposite signs. The method enhances the read precision of the sense amplifier for a given data acquisition time by doubling the differential input voltage.

Abstract: A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

Abstract: A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.

Abstract: A circuit for detecting a logic transition is proposed.

Abstract: A circuit for biasing an input node of a sense amplifier is proposed. The circuit includes a voltage regulator for keeping the input node at a pre-set operative voltage during a sensing operation. The circuit further includes a pulling device for pulling the input node from a starting voltage towards a power supply voltage, the operative voltage being comprised between the starting voltage and the power supply voltage. The circuit also includes a control device for disabling the pulling device before the input node reaches the operative voltage.

Abstract: A sense amplifier structure for multi-level non-volatile memories reads the contents of the memory cells. In particular, a current drawn by a memory cell to be read is compared to a current drawn by a reference cell through a sense amplifier that has one input terminal connected to a circuit node to which said currents are led. Advantageously, the currents are compared at both inputs of the sense amplifier by connecting a second input of said amplifier to a circuit node to which said currents are led, with opposite signs. The method enhances the read precision of the sense amplifier for a given data acquisition time by doubling the differential input voltage.