Abstract: A method and apparatus for augmenting an external voltage regulator with a shunt integrated voltage regulator is disclosed. In one embodiment, an integrated circuit (IC) includes a load circuit coupled to a supply voltage node. The supply voltage node is electrically coupled to receive a supply voltage from an external voltage regulator. The IC also includes a shunt integrated voltage regulator coupled to the supply voltage node and implemented on the same IC die as the load circuit. If the supply voltage falls below a specified value (e.g., to increased current demand), the integrated voltage regulator may begin supplying current to the load. This may cause the supply voltage to return to within its specified range of the specified value, while allowing the external voltage regulator sufficient time to respond to the increased current demand. Thus, voltage droops on the supply voltage node may be minimized.

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

Abstract: A voltage regulator includes a pass element having a control input coupled to a control node and operable to generate an output voltage at an output node, a negative feedback amplifier operable to receive a reference voltage and the output voltage and generate a signal at the control node based on a difference between the reference voltage and the output voltage, and a noise cancellation circuit coupled to the control node and the output node and operable to generate a bias current at the control node based on the output voltage.

Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Abstract: Methods and systems for simulating a system model are provided. The method includes loading into a computing system the system model that includes a plurality of event generating device models and non-event generating device models, scheduling a next event for each of the event generating device models independent of the next event of each other of the device models, advancing time to an earliest of the scheduled next events that is scheduled at a host device, committing the earliest of the scheduled next events, and replacing the earliest of the scheduled next events with a new next event for the host device.

Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.

Abstract: A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

Abstract: A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

Abstract: A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Abstract: An in-band configuration technique configures a data communications link for high-speed data communications between at least a first and second integrated circuit using in-band communications between the first and second integrated circuits. The technique configures at least one equalizer of the data communications link with predetermined equalizer settings selected from a plurality of predetermined equalizer settings based on a selected rate of data communications for the link.

Abstract: An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.

Abstract: A driver circuit that consumes less current than other driver circuits combines a current-mode driver circuit with a voltage-mode driver circuit to provide impedance matching and signal equalization operations. In at least one embodiment of the invention, an apparatus includes a differential node and a driver circuit configured to generate a signal on the differential node. The driver circuit includes a first circuit portion configured to generate a first signal on the differential node based, at least in part, on a data signal. The first signal has a voltage swing based, at least in part, on a voltage on a power supply node. The driver circuit includes at least a second circuit portion configured to generate a current through the differential node based, at least in part, on a first bit-time of the data signal and an equalization operation, thereby adjusting the voltage swing of the signal.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A pseudo bandgap voltage reference circuit includes a first transistor and a second transistor, each coupled to a supply voltage node. The circuit also includes an amplifier circuit coupled to a gate terminal of each of the first and the second transistors, a current source coupled to the supply voltage node, and a first diode coupled between the current source and a ground reference node. A first input of the amplifier circuit is coupled to a node between the current source and the first diode. In addition, a first terminal of the first transistor is coupled to a second input of the amplifier circuit in a feedback loop. Also, an output reference voltage is developed at an output node coupled to a second terminal of the second transistor. Further, an output current of the current source is independent of a current flowing through the first terminal of the first transistor.

Abstract: A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.

Abstract: An AC coupled receiver incorporates a decision feedback restore technique that is readily implemented on a monolithic integrated circuit to reduce or eliminate effects of baseline wander in a non-return-to-zero (NRZ) data receiver. In at least one embodiment of the invention, a method includes at least substantially attenuating at least a DC portion of a received signal to generate a first signal. The method includes generating a low frequency signal based at least in part on a reference signal selected from a plurality of reference signals. The method includes generating a restored signal based at least in part on the first signal and the low frequency signal.

Abstract: A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.