Patents by Inventor Emilio Yero

Emilio Yero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200126936
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
  • Publication number: 20200006268
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
  • Patent number: 10522489
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
  • Patent number: 9715913
    Abstract: Techniques and circuitry are presented for more rapidly and accurately obtaining a temperature code (TCO) on an integrated circuit. A comparison voltage is ramped up and two counts are determined concurrently, a first count on how many clock cycles for the comparison voltage to ramp up from a low reference voltage to a proportional to absolute temperature (PTAT) and a second count for the number of clock cycles for the comparison voltage to go from the low reference voltage to a high reference voltage. The TCO value is then obtained by using the second count in a post-processing calibration to adjust the first count. An initial calibration can also be included when the circuit is powered up.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 25, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jiang Yin, Jongmin Park, Emilio Yero, Steve Choi
  • Publication number: 20160124664
    Abstract: A non-volatile flash memory has bit lines spanning multiple blocks grouped into columns, where each block is connected along multiple regular columns and one or more redundancy columns. When there is a local column defect, so that the defect is not at the level of the whole block or global column, the portions of a column at an individual block can be remapped to a portion of the same block along a redundant column. Sections of multiple columns from different blocks can be remapped to the same redundancy column.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 5, 2016
    Inventors: Jagdish Sabde, Sagar Magia, Emilio Yero
  • Patent number: 8184479
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 22, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Emilio Yero
  • Patent number: 8180994
    Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 15, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Steven Sprouse, Jianmin Huang, Chris Avila, Yichao Huang, Emilio Yero
  • Patent number: 8094492
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: January 10, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Emilio Yero
  • Publication number: 20110310671
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 22, 2011
    Inventors: Dana Lee, Emilio Yero
  • Patent number: 7936602
    Abstract: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: May 3, 2011
    Assignee: SanDisk Corporation
    Inventors: Yan Li, Emilio Yero
  • Publication number: 20110075477
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Inventors: Dana Lee, Emilio Yero
  • Publication number: 20110010484
    Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.
    Type: Application
    Filed: July 8, 2009
    Publication date: January 13, 2011
    Inventors: Steven Sprouse, Jianmin Huang, Chris Avila, Yichao Huang, Emilio Yero
  • Patent number: 7869273
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: January 11, 2011
    Assignee: SanDisk Corporation
    Inventors: Dana Lee, Emilio Yero
  • Publication number: 20090262578
    Abstract: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.
    Type: Application
    Filed: June 30, 2009
    Publication date: October 22, 2009
    Inventors: Yan Li, Emilio Yero
  • Patent number: 7577037
    Abstract: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: August 18, 2009
    Assignee: SanDisk Corporation
    Inventors: Yan Li, Emilio Yero
  • Publication number: 20090059660
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 5, 2009
    Inventors: Dana Lee, Emilio Yero
  • Patent number: 7467253
    Abstract: A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: December 16, 2008
    Assignee: SanDisk Corporation
    Inventor: Emilio Yero
  • Patent number: RE43870
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: December 25, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Emilio Yero
  • Patent number: RE45771
    Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 20, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Steven Sprouse, Jianmin Huang, Chris Avila, Yichao Huang, Emilio Yero
  • Patent number: RE45813
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 24, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Dana Lee, Emilio Yero