Patents by Inventor Emilio Yero
Emilio Yero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7467253Abstract: A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.Type: GrantFiled: April 13, 2006Date of Patent: December 16, 2008Assignee: SanDisk CorporationInventor: Emilio Yero
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Patent number: 7451264Abstract: A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.Type: GrantFiled: April 13, 2006Date of Patent: November 11, 2008Assignee: SanDisk CorporationInventor: Emilio Yero
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Publication number: 20070245068Abstract: A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.Type: ApplicationFiled: April 13, 2006Publication date: October 18, 2007Inventor: Emilio Yero
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Publication number: 20070245067Abstract: A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.Type: ApplicationFiled: April 13, 2006Publication date: October 18, 2007Inventor: Emilio Yero
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Publication number: 20070109867Abstract: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.Type: ApplicationFiled: January 3, 2007Publication date: May 17, 2007Inventors: Yan Li, Emilio Yero
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Patent number: 7206230Abstract: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.Type: GrantFiled: April 1, 2005Date of Patent: April 17, 2007Assignee: SanDisk CorporationInventors: Yan Li, Emilio Yero
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Publication number: 20060221704Abstract: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.Type: ApplicationFiled: April 1, 2005Publication date: October 5, 2006Inventors: Yan Li, Emilio Yero
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Patent number: 6418051Abstract: A non-volatile memory device with configurable row redundancy includes a non-volatile memory having a matrix of memory cells and a matrix of redundant memory cells, both organized into rows and columns. The memory device also includes row and column decoding circuits; read and modify circuits for reading and modifying data stored in the memory cells; and at least one associative memory matrix, also organized into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix. The memory device further includes a circuit for recognizing and comparing selected row addresses with faulty row addresses contained in the associative memory matrix, such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and a configuration register, also comprising a matrix of non-volatile memory cells, and associated control circuits.Type: GrantFiled: February 14, 2001Date of Patent: July 9, 2002Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Manstretta, Rino Micheloni, Andrea Pierin, Emilio Yero
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Patent number: 6396168Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.Type: GrantFiled: February 12, 2001Date of Patent: May 28, 2002Assignee: STMicroelectronics S.r.l.Inventors: Stefano Ghezzi, Donato Ferrario, Emilio Yero, Giovanni Campardo
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Publication number: 20020001237Abstract: A non-volatile memory device with configurable row redundancy includes a non-volatile memory having a matrix of memory cells and a matrix of redundant memory cells, both organized into rows and columns. The memory device also includes row and column decoding circuits; read and modify circuits for reading and modifying data stored in the memory cells; and at least one associative memory matrix, also organized into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix. The memory device further includes a circuit for recognizing and comparing selected row addresses with faulty row addresses contained in the associative memory matrix, such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and a configuration register, also comprising a matrix of non-volatile memory cells, and associated control circuits.Type: ApplicationFiled: February 14, 2001Publication date: January 3, 2002Inventors: Alessandro Manstretta, Rino Micheloni, Andrea Pierin, Emilio Yero
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Publication number: 20010030554Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.Type: ApplicationFiled: February 12, 2001Publication date: October 18, 2001Applicant: STMicroelectronics S.r.l.Inventors: Stefano Ghezzi, Donato Ferrario, Emilio Yero, Giovanni Campardo
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Patent number: 6140876Abstract: In a differential amplifier with asymmetrical outputs, the gates of the two load transistors are at the same specified potential and the voltage at the connection node between the load transistor and the amplifier transistor of one arm is stabilized by means of a compensation structure. This amplifier works at low VCC (e.g., less than 2 volts) while at the same time having high gain.Type: GrantFiled: November 6, 1998Date of Patent: October 31, 2000Assignee: STMicroelectronics S.A.Inventor: Emilio Yero
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Patent number: 5923590Abstract: A device for the reading of cells for a memory includes a high-gain current comparison circuit, including a first arm for the reproduction, by current mirror, of the reference current conducted by a reference cell and a second arm for the reproduction, by current mirror, of the read current of a selected memory cell. A current mirror structure is provided to reproduce the current of the first arm in the second arm so as to obtain the comparison and produce a representative voltage level at output.Type: GrantFiled: June 12, 1997Date of Patent: July 13, 1999Assignee: SGS-Thomson Microelectronics S.A.Inventor: Emilio Yero
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Patent number: 5699295Abstract: In a memory in integrated circuit form, organized as a matrix of rows and columns, a current detection circuit is connected at input to at least one column of the memory and at output to a corresponding read circuit. The current detection circuit includes a transistor connected between the input and the output and controlled at its gate by a reference current detection circuit.Type: GrantFiled: May 17, 1996Date of Patent: December 16, 1997Assignee: SGS-Thomson Microelectronics S.A.Inventor: Emilio Yero
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Patent number: 5675539Abstract: An integrated circuit memory that contains a device for the precharging and reading of the bit lines, including a precharging element, a current-voltage converter and a read circuit, further contains a test circuit to isolate the output of the converter from the precharging element and from the read circuit, to apply a test voltage to a cell of the memory through the converter and to measure the current in the cell.Type: GrantFiled: December 21, 1995Date of Patent: October 7, 1997Assignee: SGS-Thomson Microelectronics, S.A.Inventors: Jean-Michel Mirabel, Emilio Yero
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Patent number: 5469382Abstract: A device is provided for detecting the content of cells of a memory, and for minimizing the read access time of a high-capacity EPROM memory in which cells are organized as a set of bit rows. A comparator including a differential amplifier compares a reference current from a reference column with a read current invoked in a cell of a bit row. The reference current and a read current flow through a resistive reference element and a resistive read element respectively. These resistive elements are connected, at one end, to a supply voltage source and, at the other end, to the non-inverting input and the inverting input respectively of the differential amplifier. The differential amplifier delivers as output a detection signal. In a preloading period the output of the differential amplifier is connected to its inverting input.Type: GrantFiled: June 11, 1993Date of Patent: November 21, 1995Assignee: SGS-Thomson Microelectronics S.A.Inventor: Emilio Yero
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Patent number: 5412602Abstract: A device for generating a voltage for programming a programmable permanent memory, especially of EPROM type, from an external DC voltage source, the device including a circuit for generating a reference voltage, a circuit for duplicating the reference voltage which is arranged as a current and voltage mirror and which outputs a programing voltage as its output, and a follower MOS transistor whose drain and source are connected respectively to the external DC voltage source and to the output of the duplicating means and whose gate is connected to a predetermined internal node of the circuit for generating a reference voltage.Type: GrantFiled: November 3, 1993Date of Patent: May 2, 1995Assignee: SGS-Thomson Microelectronics S.A.Inventor: Emilio Yero
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Patent number: 5406141Abstract: A high-voltage switching circuit comprising two arms, wherein each arm has a P-channel load transistor, a forward biased diode and an N-channel switching transistor series-connected between the high voltage and the ground. The gate of the N-channel transistor is controlled by a switching signal C in one arm and by the complementary switching signal C in the other arm. Such a structure enables the stress undergone by the load and switching transistors of the switching circuit to be reduced by several magnitudes.Type: GrantFiled: July 6, 1993Date of Patent: April 11, 1995Assignee: SGS-Thomson Microelectronics, S.A.Inventors: Emilio Yero, Olivier Rouy
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Patent number: 5331599Abstract: An integrated circuit memory which includes a subcircuit for generating a programmable reference voltages on-chip from an external high-voltage supply line. Depending on the mode of operation (test, read, write, etc.), the reference voltage is changed.Type: GrantFiled: March 17, 1993Date of Patent: July 19, 1994Assignee: SGS-Thomson Microelectronics, S.A.Inventor: Emilio Yero
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Patent number: 5303189Abstract: An erasable and electrically programmable memory with only few cells works at high speed in reading mode and is reliable. This is achieved by using a voltage limiter that limits the variation in the drain voltage of the memory cells.Type: GrantFiled: March 1, 1991Date of Patent: April 12, 1994Assignee: SGS-Thomson Microelectronics S.A.Inventors: Jean Devin, Emilio Yero, Claude Costabello