Patents by Inventor Emmett M. Kilgariff

Emmett M. Kilgariff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12045924
    Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: July 23, 2024
    Assignee: NVIDIA Corporation
    Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
  • Publication number: 20230007920
    Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 12, 2023
    Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
  • Patent number: 11481950
    Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: October 25, 2022
    Assignee: NVIDIA Corporation
    Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
  • Publication number: 20210174569
    Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.
    Type: Application
    Filed: January 29, 2021
    Publication date: June 10, 2021
    Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
  • Patent number: 10909738
    Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 2, 2021
    Assignee: NVIDIA Corporation
    Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
  • Publication number: 20190213775
    Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 11, 2019
    Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
  • Patent number: 10068366
    Abstract: A method, computer readable medium, and system are disclosed for generating multi-view image data. The method includes the steps of processing primitive data of a model to generate processed primitive data that includes multiple position vectors for each vertex in the primitive data, the number of position vectors associated with each vertex being equal to the number of views in at least two views being generated. The method further includes storing the processed primitive data in a buffer. Finally, the processed primitive data may be read from the buffer for each view in the at least two views and transmitted to a raster pipeline to generate image data corresponding to a particular view.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 4, 2018
    Assignee: NVIDIA Corporation
    Inventors: Ziyad Sami Hakura, Eric B. Lum, Henry Packard Moreton, Emmett M. Kilgariff
  • Patent number: 9922457
    Abstract: A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 20, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Justin S. Legakis, Emmett M. Kilgariff, Michael C. Shebanow
  • Patent number: 9830741
    Abstract: Techniques are disclosed for processing graphics objects in a stage of a graphics processing pipeline. The techniques include receiving a graphics primitive associated with the graphics object, and determining a plurality of attributes corresponding to one or more vertices associated with the graphics primitive. The techniques further include determining values for one or more state parameters associated with a downstream stage of the graphics processing pipeline based on a visual effect associated with the graphics primitive. The techniques further include transmitting the state parameter values to the downstream stage of the graphics processing pipeline. One advantage of the disclosed techniques is that visual effects are flexibly and efficiently performed.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: November 28, 2017
    Assignee: NVIDIA Corporation
    Inventors: Emmett M. Kilgariff, Morgan McGuire, Yury Y. Uralsky, Ziyad S. Hakura
  • Publication number: 20170323469
    Abstract: A method, computer readable medium, and system are disclosed for generating multi-view image data. The method includes the steps of processing primitive data of a model to generate processed primitive data that includes multiple position vectors for each vertex in the primitive data, the number of position vectors associated with each vertex being equal to the number of views in at least two views being generated. The method further includes storing the processed primitive data in a buffer. Finally, the processed primitive data may be read from the buffer for each view in the at least two views and transmitted to a raster pipeline to generate image data corresponding to a particular view.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 9, 2017
    Inventors: Ziyad Sami Hakura, Eric B. Lum, Henry Packard Moreton, Emmett M. Kilgariff
  • Patent number: 9792122
    Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 17, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad S. Hakura, Walter R. Steiner, Cynthia Ann Edgeworth Allison, Rouslan Dimitrov, Karim M. Abdalla, Dale L. Kirkland, Emmett M. Kilgariff
  • Patent number: 9734548
    Abstract: One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: August 15, 2017
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Rouslan Dimitrov, Emmett M. Kilgariff, Andrei Khodakovsky
  • Patent number: 9710874
    Abstract: One embodiment of the present invention sets forth a technique for mid-primitive execution preemption. When preemption is initiated no new instructions are issued, in-flight instructions progress to an execution unit boundary, and the execution state is unloaded from the processing pipeline. The execution units within the processing pipeline, including the coarse rasterization unit complete execution of in-flight instructions and become idle. However, rasterization of a triangle may be preempted at a coarse raster region boundary. The amount of context state to be stored is reduced because the execution units are idle. Preempting at the mid-primitive level during rasterization reduces the time from when preemption is initiated to when another process can execute because the entire triangle is not rasterized.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 18, 2017
    Assignee: NVIDIA Corporation
    Inventors: Gregory Scott Palmer, Ziyad S. Hakura, Emmett M. Kilgariff, Dale L. Kirkland, Lacky V. Shah
  • Patent number: 9697641
    Abstract: One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: July 4, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Steven E. Molnar, Emmett M. Kilgariff, Walter E. Donovan, Christian Amsinck, Robert Ohannessian
  • Patent number: 9659399
    Abstract: A system, method, and computer program product are provided for passing attribute structures between shader stages of a processing pipeline. The method includes the steps of receiving data represented at a first level by a processing pipeline including an upstream shader unit, a downstream shader unit, and a processing unit. The upstream shader unit processes the data to generate a first set of attributes corresponding to the data represented at a second level. The upstream shader unit also stores the first set of the attributes in a first portion of a memory system that can be read by the downstream shader unit and any shader units that are downstream in the processing pipeline relative to the upstream shader unit. In one embodiment, the processing unit is coupled between the upstream shader unit and the downstream shader unit.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: May 23, 2017
    Assignee: NVIDIA Corporation
    Inventors: Ziyad Sami Hakura, Henry Packard Moreton, Emmett M. Kilgariff
  • Patent number: 9542189
    Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 10, 2017
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Cynthia Ann Edgeworth Allison, Joseph Cavanaugh, Dale L. Kirkland, Emmett M. Kilgariff
  • Patent number: 9536341
    Abstract: One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: January 3, 2017
    Assignee: NVIDIA Corporation
    Inventors: Johnny S. Rhoades, Emmett M. Kilgariff, Michael C. Shebanow, Ziyad S. Hakura, Dale L. Kirkland, James Daniel Kelly
  • Patent number: 9529712
    Abstract: Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: December 27, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Brian Kelleher, Emmett M. Kilgariff, Wayne Yamamoto
  • Patent number: 9436969
    Abstract: One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle. The smaller tasks do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second cycle are balanced and make full use of resources. Therefore, the performance of the tessellation and geometry shaders is improved.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: September 6, 2016
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Emmett M. Kilgariff, Dale L. Kirkland, Johnny S. Rhoades, Cynthia Ann Edgeworth Allison, Karim M. Abdalla
  • Patent number: 9411596
    Abstract: One embodiment of the present invention sets forth a graphics subsystem. The graphics subsystem includes a first tiling unit associated with a first set of raster tiles and a crossbar unit. The crossbar unit is configured to transmit a first set of primitives to the first tiling unit and to transmit a first cache invalidate command to the first tiling unit. The first tiling unit is configured to determine that a second bounding box associated with primitives included in the first set of primitives overlaps a first cache tile and that the first bounding box overlaps the first cache tile. The first tiling unit is further configured to transmit the primitives and the first cache invalidate command to a first screen-space pipeline associated with the first tiling unit for processing. The screen-space pipeline processes the cache invalidate command to invalidate cache lines specified by the cache invalidate command.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: August 9, 2016
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Emmett M. Kilgariff