Techniques for balancing accesses to memory having different memory types
Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.
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A number of electronic devices include one or more computing devices such as one or more central processing units (CPU), one or more graphics processing units (GPU), one or more digital signal processors (DSP), and/or the like. The computing device, herein after simply referred to as a processor, executes computing device readable instructions (e.g., computer programs) and operates on data stored in one or more computing device readable media, herein after simply referred to as memory. To access instructions and data stored in memory, the processor may include one or more memory controllers and one or more memory interfaces. For example, a processor 110 may include a memory controller 115 and a plurality of memory interfaces 120-135 for accessing frame buffer memory 140-155, as illustrated in
The processor also includes a number of other functional blocks not shown. For example, the processor may include a plurality of processor cores, one or more communication interfaces, and the like. Processors are well known in the art and therefore those aspects of the processor that are not germane to an understanding of the present technology will not be discussed further.
The performance of the electronic device and/or the processor of the electronic device is determined by a number of factors, including the amount of memory, the speed at which the memory can be accessed, the power consumed, and/or the like. Generally, the larger the storage capacity the more the memory costs. Similarly, the faster the memory device is, the more the memory costs and the more power the memory device consumes. Generally, the processor and memory are not utilized at peak performance most of the time. Instead, most of the time the processor and memory are idle (e.g., standby or sleep mode) or have a low workload. In addition, a manufacturer may offer a plurality of models of an electronic device based upon a common device architecture. For example, a family of graphics processors having a common device architecture may include a first model that includes 4 GB of SDDR3 (double data rate synchronous dynamic random access memory) memory operating at 1 GHz, another model may include 2 GB of GDDR5 memory operating at 2 GHz. Generally, the conventional processor and memory systems limit the ability to provide multiple models having a common device architecture that offer different levels of performance based upon memory storage capacity, memory access speed, power consumption, costs and combinations thereof. Accordingly, there is a continuing need for improved memory subsystems in computing devices such as central processing units, graphics processing units, digital signal processing units, microcontrollers, and the like.
SUMMARY OF THE INVENTIONThe present technology may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the present technology directed toward techniques for balancing memory accesses to memory having different memory types.
In one embodiment, one or more parameters, including a data rate, of a plurality of different types of memory devices coupled to a computing device are determined. A memory mapping algorithm is then configured to balance traffic to memory devices including a plurality of different memory types as a function of the one or more determined parameters including the data rate of the memory devices.
In another embodiment, for each received memory access requests, locations in a plurality of memory devices are determined. The locations are determined from a mapping that balances traffic between two or more memories of different memory types as a function of one or more parameters including a data rate of the different memory types. The locations in the corresponding memory devices may then be accessed.
Embodiments of the present technology are illustrated by way of example and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Reference will now be made in detail to the embodiments of the present technology, examples of which are illustrated in the accompanying drawings. While the present technology will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it is understood that the present technology may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present technology.
Some embodiments of the present technology which follow are presented in terms of routines, modules, logic blocks, and other symbolic representations of operations on data within one or more electronic devices. The descriptions and representations are the means used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. A routine, module, logic block and/or the like, is herein, and generally, conceived to be a self-consistent sequence of processes or instructions leading to a desired result. The processes are those including physical manipulations of physical quantities. Usually, though not necessarily, these physical manipulations take the form of one or more electric or magnetic signals capable of being stored, transferred, compared and otherwise manipulated in a electronic device. For reasons of convenience, and with reference to common usage, these signals are referred to as data, bits, values, elements, symbols, characters, terms, numbers, strings, and/or the like with reference to embodiments of the present technology.
It should be borne in mind, however, that all of these terms are to be interpreted as referencing physical manipulations and quantities and are merely convenient labels and are to be interpreted further in view of terms commonly used in the art. Unless specifically stated otherwise as apparent from the following discussion, it is understood that through discussions of the present technology, discussions utilizing the terms such as “receiving,” and/or the like, refer to the action and processes of an electronic device such as an electronic computing device that manipulates and transforms data. The data are represented as physical (e.g., electronic signals) quantities within the electronic device's logic circuits, registers, memories and/or the like, and is transformed into other data similarly represented as physical quantities within the electronic device.
In this application, the use of the disjunctive is intended to include the conjunctive. The use of definite or indefinite articles is not intended to indicate cardinality. In particular, a reference to “the” object or “a” object is intended to denote also one of a possible plurality of such objects.
Referring now to
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At 520, locations in a plurality of memory device 230-235, 335-345 are determined for the given physical address and given length from a mapping 255, 355 that balances traffic between two or more memories of different memory types as a function of one or more parameters including the data rate of the different memory types. For example, a memory write access to 6 KB starting at a given physical address may be mapped to stripe a first 1 KB chunk to a 1 GHz SDDR3 memory device coupled to a first frame buffer memory interface, a second and third 1 KB chunks to a 2 GHz GDDR5 memory device coupled to a second frame buffer memory interface, a fourth 1 KB chunk to the 10 Hz SDDR3 memory device, and a fifth and sixth 1 KB chunk to the 2 GHz GDDR5 memory device, as illustrated in
Referring again to
In one implementation, the method of initializing a processor and memory to support different memory types may be performed during the manufacturing of the computing device. For example, a manufacturer may design a family of processor having a common modular architecture that may be configured to implement a plurality of different processors or electronic circuits, such as a basic GPU, and a better GPU. The performance of the processor is determined by a number of factors, including the amount of memory, the speed at which the memory can be accessed, and the power consumed by the memory. It is difficult to predict the performance of the competitor's processor offerings. However, it would be advantageous to offer a basic GPU that out performs the competing offerings by a given amount (e.g., 20-50%). In addition, it is advantageous that the better GPU provide a given amount of additional performance over the basic GPU (e.g., 20-50% better performance). Embodiments of the present technology enable a manufacturer to choose the mix of memory coupled to the processor late in the manufacturing cycle (e.g., during circuit board assembly) to achieve a given set of performance parameters. For example, the execution speed and power consumption by the basic GPU may beat the competition's offering with two 2 GB SDDR3 memory IC operating at a 1 GHz data rate coupled to two frame buffer memory interface in a 128 bit-wide memory configuration. A processor with one 4 GB SDDR3 memory IC operating at 1 GHz and a 2 GB GDDR5 operating at 2 GHz may provide the additional processing speed, while conserving power and keeping costs lower than if two GDDR5 memory chips were used. Accordingly, a manufacturer may advantageously meet a mix of performance metrics for a product family utilizing the techniques for initializing and operation of a processor and memory supporting different memory types in accordance with embodiments of the present technology.
Referring now to
Referring now to
At optional process 720, one or more parameters of the processor 610 or loads on the processor (e.g., applications) may also be determined. The one or more parameters of the processor may include the number of memory interfaces coupling the memory to the processor in each partition, or the like. For example, it may be determined that the processor includes two frame buffer memory interfaces 620, 625, one coupled to a 1 GHz SDDR3 memory 630 and a second coupled to 2.5 GHz GDDR5 memory 635. The one or more parameters of the processing load may include a type of processing, the memory bandwidth, memory latency, the amount of memory needed, or the like. For example, the processing type may be MPEG rendering, three-dimensional rendering or the like. The memory bandwidth may be a prediction of the memory utilizations such as idle, low or high.
At 730, each memory device is organized into one or more partitions as a function of the one or more determined parameters including the data rate of each of the different type of memory devices. For example, for a 1 KB page size, 5 KB of memory may in the 2.5 GHz GDDR5 memory 635 in the same amount of time as 2 KB of the 1 GHz SDDR3 memory 630. Therefore, in the same amount of time that it takes to access the entire 1 GB of the 2.5 GHz GDDR memory 635, only 0.4 GB of 1 GB, 1 GHz SDDR3 memory can be accessed. Accordingly, the 1 GB, 1 GHz SDDR3 memory 630 may be organized into a 0.4 GB partition (P0) and a 0.6 GB partition (P2), and the 1 GB, 2.5 GHz GDDR5 memory 635 may be organized into a 1 GB partition (P1).
At 740, a memory mapping algorithm 640 is configured to balance traffic to partitions in the memory devices of two or more different memory types 630, 635 as a function of the one or more determined parameters including the data rate. In one implementation, the memory mapping algorithm 640 is configured to generate a memory map 645 that balances traffic between a plurality of partitions having different data rates. The traffic may be balanced by striping memory access across the plurality of partitions as a function of the different data rates of the memory devices. For example, if 1 GB of 1 GHz SDDR3 630 and 1 GB of 2.5 GHz GDDR5 635 are coupled to the processor 610, the mapping algorithm may be configured to store data in a first partition of 0.4 GB of the 1 GHz SDDR3 memory 630 and a second partition of 1 GB of the 2.5 GDDR6 memory 635 at a ratio of 2:5, and a third partition of 0.6 GB of the 1 GHz SDDR3 memory 630. The data may be striped across the first P0 and second partitions P1. The leftover memory of the third partition P2 may be mapped separately, non-striped, so that all the memory is accessible.
At 750, the memory mapping algorithm 640 may be dynamically configured to balance traffic to partitions in memory devices of the two or more different memory types further as a function of one or more other determined parameters. For example, the memory mapping algorithm 640 may be dynamically configured to direct memory accesses to the third partition if a memory access traffic load parameter is in a predetermined range, such as MPEG decoding, idle or low processing load. While for a second type of processing or second memory bandwidth requirement, such as three-dimensional rendering or a high processing load, the mapping algorithm is configured to direct memory accesses to the first and second partitions as a function of the data rate of each partition. Alternatively or in addition, the memory mapping algorithm 640 may be dynamically configured to direct memory accesses to the first and third partitions if a power consumption parameter is in a predetermined range, such as when operating on a battery instead of plugged into an electrical outlet.
Referring now to
At 820, locations in a plurality of memory device 630, 635 are determined for the given physical address and given length from a mapping 645 that balances traffic between partitions in the memory devices of two or more different memory types as a function of one or more parameters including the data rate of the different memory types. For example, as illustrated in
At 830, one or more memory interfaces 620, 62 are used to access the locations in the corresponding memory devices 630, 635 of different memory types. In one implementation, the memory controller 615 dispatches the memory access requests to the given memory interfaces 620, 625 determined from the memory mapping table 645 as a function of one or more parameters, including the data rate of the different memory types.
Embodiments of the present technology may be readily extended to electronic devices having memory systems that include more than two different types of memory. For example, the memory accesses may be striped across three memories, until one or the memories runs out. The memory accesses may then be stripped over the other two memories, until a second memory runs out. Thereafter, the memory accesses may to the third memory device in a non-striped manner. In addition, embodiments of the present technology may be readily extended to electronic device having memory systems that include different types of memory that have non-integer ratios between the respective data rates.
The foregoing descriptions of specific embodiments of the present technology have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, to thereby enable others skilled in the art to best utilize the present technology and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
Claims
1. A method comprising: determining one or more parameters, including a data access rate, of a plurality of different types of memory devices coupled to a computing device;
- and configuring a memory mapping algorithm to balance traffic to two or more memory devices of different types together for a given memory access as a function of the one or more determined parameters including the data access rates of the two or more memory devices of different types and to stripe memory accesses for a first location in an address space across the two or more memory devices of different types in a ratio of the data access rate of the two or more memory devices of different types.
2. The method according to claim 1, further comprising configuring the memory mapping algorithm to dynamically access memories of one or more types as a function of one or more other determined parameters.
3. The method according to claim 1, further comprising:
- determining one or more parameters of the computing device or load on the computing device; and
- configuring the memory mapping algorithm to dynamically access memory of one or more types as a function of one or more determined parameters of the computing device or load on the computing device.
4. The method according to claim 1, further comprising: organizing each memory device into one or more partitions as a function of the one or more determined parameters including the data rate of the memory devices;
- and configuring the memory mapping algorithm to balance traffic to partitions in the two or more memory devices of two or more different types together for the given memory access as a function of the one or more determined parameters including the data rate of the memory devices.
5. The method according to claim 1, wherein the memory mapping is configured to access a leftover portion, after striping, of a first or second of the two or more memory devices, wherein the leftover portion of the first or second of the two or more memory devices is accessed, at a second location in the address space, as contiguous memory and not striped memory.
6. A method comprising: receiving a memory access request at a given physical address and a given length;
- Determining locations in a plurality of memory devices for the given physical address and the given length from a mapping, wherein the mapping balances traffic between two or more memories of different memory types together for the memory access request as a function of one or more parameters including a data access rate of the different memory types and stripes memory accesses for a first location in an address space across the two or more memory devices of different types in a ratio of the data access rate, of the two or more memory device of different types;
- And accessing the locations in the corresponding memory device.
7. The method according to claim 6, wherein the mapping further balances traffic between partitions in the two or more memories of different types together for the memory access request as a function of one or more parameters including a data rate of the different memory types.
8. The method according to claim 6, wherein the plurality of memory devices comprises a first set of memory devices operating at first data rate and a second set of memory devices operating at a second data rate.
9. The method according to claim 8, wherein the locations for write memory accesses are dynamically mapped to memories of one or more types as a function of one or more other parameters for another memory access request instead of balanced as a function of the data rate of the different memory types.
10. The method according to claim 9, wherein the one or more other parameters include a memory access traffic load parameter.
11. The method according to claim 9, wherein the one or more other parameters include a memory power consumption parameter.
12. A method comprising:
- an initialization phase including: determining one or more parameters, including a data rate, of a plurality of memory devices including memory devices of two or more different types coupled to a computing device; and configuring a memory mapping algorithm to balance traffic between memory devices of first and second types together for a give memory access as a function of the one or more determined parameters including the data rate of the memory devices of the first and second types and to stripe memory accesses across the memory devices of the first and second types in a ratio of the data rates of the first and second types; and
- an operating phase including: receiving a memory access request at a given physical address and a given length; determining location in one or more of the memory devices for the given physical address and the given length based on the memory mapping algorithm; and
- accessing the locations in the one or more memory devices.
13. The method according to claim 12, wherein memory of the first type is characterized by a first data rate, and memory of the second type is characterized by a second data rate that is faster than the first data rate.
14. The method according to claim 13, wherein memory of the first type is characterized by a first storage capacity, and memory of the second type is characterized by a second storage capacity that is less than the first storage capacity.
15. The method according to claim 14, wherein memory of the first type is characterized by a first power rate, and memory of the second type is characterized by a second power rate that is greater than the first power rate.
16. The method according to claim 15, wherein memory of the first type is characterized by a first cost, and memory of the second type is characterized by a second cost that is greater than the first cost.
17. The method according to claim 12, wherein the configured memory mapping algorithm dynamically accesses memory of the first type if a memory access traffic load parameter is in a predetermined range, instead of balancing traffic between memory of the first and second types.
18. The method according to claim 12, wherein the configured memory mapping algorithm dynamically accesses memory of the first type if a power consumption parameter is in a predetermined range, instead of balancing traffic between memory of the first and second types.
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Type: Grant
Filed: Jul 26, 2011
Date of Patent: Dec 27, 2016
Patent Publication Number: 20130031328
Assignee: NVIDIA CORPORATION (Santa Clara, CA)
Inventors: Brian Kelleher (Palo Alto, CA), Emmett M. Kilgariff (San Jose, CA), Wayne Yamamoto (Saratoga, CA)
Primary Examiner: Mardochee Chery
Assistant Examiner: Khoa D Doan
Application Number: 13/191,438
International Classification: G06F 12/08 (20060101); G06F 12/02 (20060101); G06F 12/06 (20060101); G06F 13/16 (20060101);