Patents by Inventor Emre Ayranci

Emre Ayranci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10771025
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Publication number: 20200266778
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Publication number: 20200220508
    Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Publication number: 20200220567
    Abstract: Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10700658
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 30, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Patent number: 10700650
    Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: June 30, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10686409
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 16, 2020
    Assignee: pSemi Corporation
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Patent number: 10673401
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 2, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20200144967
    Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 7, 2020
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20200127618
    Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 23, 2020
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20190372528
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 5, 2019
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Publication number: 20190363690
    Abstract: A front end module (FEM) and associated method for receiving signals in a front end module are disclosed. Some embodiments of the FEM have three inputs. The FEM can process the input signals in one of three bypass modes. In bypass modes, switchable tank circuits provide a high impedance to isolate active components from the bypass path. This improves the input return loss in the passive bypass mode and thus improves the performance of the passive bypass mode by allowing the use of LNAs without an input switch. In the active gain mode, one of a plurality of signals are amplified by one of an equal number of amplifiers coupled to the FEM output. Accordingly, the FEM can output signals applied to any one of the FEM inputs in bypass mode, or an amplified version of one of the input signals. In some embodiments, the FEM has only one input and one LNA. In such embodiments, an output selector switch selects between a bypass path and a gain path.
    Type: Application
    Filed: November 27, 2018
    Publication date: November 28, 2019
    Inventors: Joseph Golat, David Kovac, Emre Ayranci, Miles Sanner
  • Patent number: 10491164
    Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: November 26, 2019
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 10476453
    Abstract: A front end circuit architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 12, 2019
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 10381991
    Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 13, 2019
    Assignee: pSemi Corporation
    Inventors: Miles Sanner, Emre Ayranci
  • Publication number: 20190245497
    Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 8, 2019
    Inventors: Miles Sanner, Emre Ayranci
  • Patent number: 10326484
    Abstract: A front end module having reduced number of low noise amplifier (LNAs) for receiving various combinations of contiguous aggregation (CA) signals and non-CA signals having different combinations of signals aggregated therein. The FECC can include a broadband LNA and/or a band-switching LNA having at least two modes of operation. An input switch directs a received signal to one of several banks of filters. LNA switches direct the signals from the output of filters within a selected filter bank to particular LNAs. LNAs may be connected by LNA switches to filters in more than one filter bank. The proper mode of operation is selected for the band switching LNA based on the particular frequencies present in the received signal and the filters selected.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 18, 2019
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli, Kashish Pal
  • Patent number: 10250199
    Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 2, 2019
    Assignee: pSemi Corporation
    Inventors: Jonathan Klaren, Poojan Wagh, David Kovac, Eric S. Shapiro, Neil Calanca, Dan William Nobbe, Christopher Murphy, Robert Mark Englekirk, Emre Ayranci, Keith Bargroff, Tero Tapio Ranta
  • Patent number: 10199996
    Abstract: A high performance low noise amplifier integrated circuit having multiple low noise amplifiers enabling operation over a wide range for frequencies is disclosed. In particular, an auxiliary input is provided to the low noise amplifier integrated circuit that can be routed to one of several low noise amplifiers, each tuned to operate efficiently in different frequency ranges.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: February 5, 2019
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Edward Nicholas Comfoltey
  • Publication number: 20190020322
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 17, 2019
    Inventors: Emre Ayranci, Miles Sanner