Patents by Inventor Emre Ayranci

Emre Ayranci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12368417
    Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: July 22, 2025
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20250150052
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Application
    Filed: January 11, 2025
    Publication date: May 8, 2025
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Publication number: 20250080070
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 12237821
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: February 25, 2025
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Patent number: 12218637
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: February 4, 2025
    Assignee: pSemi Corporation
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Patent number: 12212291
    Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: January 28, 2025
    Assignee: pSemi Corporation
    Inventors: Miles Sanner, Emre Ayranci
  • Patent number: 12191819
    Abstract: Methods and devices for realizing RF processing paths associated to different frequency bands are presented. According to one aspect, the RF processing paths are provided by a hybrid input LNA RF frontend that includes RF processing paths that are dedicated to specific frequency bands and RF processing paths that are shared between several frequency bands. Sharing of the RF processing paths is provided by an input combiner network and/or a multi-input cascode amplifier that includes a cascode transistor that is coupled to at least two input transistors. Further presented in a toolkit that includes circuit blocks that can be used in specific combinations to customize the RF processing paths to achieve specific performance or cost optimization. A decision tree based on performance and cost priorities assigned to each of the frequency bands is used to provide the specific combinations.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 7, 2025
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 12184248
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 31, 2024
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 12176936
    Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: December 24, 2024
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 12170506
    Abstract: A low noise amplifier (LNA) with configurable feedback that includes a filter circuit for improved stability is presented. The filter circuit includes an L-C tank. The filter circuit further includes a resistor in parallel with the L-C tank. The filter circuit is tunable/adjustable/programmable. The filter circuit further includes a capacitor selectively arranged in parallel with the L-C tank. The filter circuit is coupled to an input of the LNA via a series resistor. The filter circuit is coupled between the input and an output of the LNA via one or more switches. The LNA includes a first stage with a common-source transistor and a common-gate transistor. The LNA further includes a wideband feedback circuit coupled between the input and output of the first stage. The LNA includes a source-follower circuit. The source follower circuit is configurable as a second stage, or a feedback circuit, coupled to the filter circuit.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: December 17, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Emre Ayranci, Mengsheng Rui, Miles Sanner, Anant Rungta
  • Patent number: 12149213
    Abstract: Circuits and methods for a multi-gain mode amplifier, particularly an LNA, that achieves wideband output impedance matching and high gain while maintaining low power and a low NF in a highest gain mode, and which can switch to one or more lower gain modes that achieve higher linearity with lower power. In a highest gain mode, an inductor is selectively inserted between the amplified-signal terminal of an amplification core and an output LC output matching network. The inductor, when inserted, provides wideband output impedance matching, functioning as a series peaking inductor; accordingly, the inserted inductor delays current flow to the output capacitor and lowers the rise time of signal changes across the output capacitor. In addition, higher gain can be achieved compared to a conventional LC output impedance matching topology due to a higher impedance at the amplified-signal terminal of the amplification core.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: November 19, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Emre Ayranci, Mengsheng Rui, Jubaid Qayyum
  • Publication number: 20240364269
    Abstract: A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.
    Type: Application
    Filed: May 2, 2024
    Publication date: October 31, 2024
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 12113485
    Abstract: Methods and devices for reducing DC current consumption of a multi-stage LNA amplifier. According to one aspect, first and second amplification stages are stacked to provide a common conduction path of a DC current. The first stage includes a common-source amplifier, the second stage includes a common-drain amplifier. Coupling between the two stages is provided by series connection of load inductors of the respective stages and a capacitor coupled at a common node between the inductors. According to another aspect, a current splitter circuit is used to split a current to the first stage according to two separate conduction paths, one common path to the two stages, and another separate from the second stage. According to yet another aspect, the current splitter circuit includes a feedback loop that controls the splitting of the current so to maintain a constant current through the common path.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: October 8, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Emre Ayranci, Miles Sanner, Mengsheng Rui, Jubaid Qayyum
  • Patent number: 12101065
    Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: September 24, 2024
    Assignee: pSemi Corporation
    Inventors: Miles Sanner, Emre Ayranci, Parvez Daruwalla
  • Publication number: 20240243706
    Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Application
    Filed: March 28, 2024
    Publication date: July 18, 2024
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20240186958
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Application
    Filed: December 8, 2023
    Publication date: June 6, 2024
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Publication number: 20240171145
    Abstract: A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 23, 2024
    Inventors: Jing Li, Emre Ayranci, Miles Sanner
  • Patent number: 11984855
    Abstract: A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: May 14, 2024
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20240146272
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 11967935
    Abstract: Methods and systems for a multi gain LNA architecture achieving minimum phase discontinuity between all the different active and passive gain modes that uses different LNA configurations and settings for single and multi-stage LNAs by a configurable combined output matching and phase adjusting circuitry.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 23, 2024
    Assignee: PSEMI CORPORATION
    Inventors: Emre Ayranci, Phanindra Yerramilli