Patents by Inventor Emre Ayranci

Emre Ayranci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180083578
    Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: Jonathan Klaren, Poojan Wagh, David Kovac, Eric S. Shapiro, Neil Calanca, Dan William Nobbe, Christopher Murphy, Robert Mark Englekirk, Emre Ayranci, Keith Bargroff, Tero Tapio Ranta
  • Publication number: 20180019710
    Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
    Type: Application
    Filed: November 2, 2016
    Publication date: January 18, 2018
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 9774303
    Abstract: A low noise amplifier (LNA) system for amplifying a plurality of carriers includes a first amplifier circuit that generates a first radio-frequency (RF) output signal by amplifying a first input RF signal corresponding to a first frequency band, the first amplifier circuit having a first input impedance, and a second amplifier circuit that generates a second RF output signal by amplifying the first input RF signal when the system is in a first multi-output mode, a second input impedance of the second amplifier having a first impedance value when the system is in the first multi-output mode. The LNA system further includes a first impedance controller that maintains the second input impedance of the second amplifier circuit at a second impedance value when the apparatus is in a mode other than the first multi-output mode. The second impedance value is substantially the same as the first impedance value.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: September 26, 2017
    Assignee: Marvell International Ltd.
    Inventors: Emre Ayranci, Marco Garampazzi, Shahrzad Tadjpour