Abstract: Embodiments of 3D memory devices with a semiconductor plug protected by a dielectric layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the memory stack. The memory string includes a semiconductor plug in a lower portion of the memory string, a protective dielectric layer on the semiconductor plug, and a memory film above the protective dielectric layer and along a sidewall of the memory string.

Abstract: Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.

Abstract: Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.

Abstract: Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.

Abstract: Embodiments of 3D memory devices with a semiconductor plug protected by a dielectric layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the memory stack. The memory string includes a semiconductor plug in a lower portion of the memory string, a protective dielectric layer on the semiconductor plug, and a memory film above the protective dielectric layer and along a sidewall of the memory string.

Abstract: A semiconductor device includes a string of transistors stacked along a vertical direction above a substrate of the semiconductor device. The string can include a first substring, a channel connector disposed above the first substring, and a second substring. The first substring includes a first channel structure having a first channel layer and a first gate dielectric structure that extend along the vertical direction. The second substring is stacked above the channel connector, and has a second channel structure that includes a second channel layer and a second gate dielectric structure that extend along the vertical direction. The channel connector, electrically coupling the first and the second channel layer, is disposed below the second gate dielectric structure to enable formation of a conductive path in a bottom region of the second channel layer. The bottom region is associated with a lowermost transistor in the second substring.

Abstract: In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Embodiments of the present application disclose a data transmission method and system, and a related apparatus. The method in the embodiments of the present application includes: when a network-side data transmission apparatus detects that a terminal is handed over from being served by a source base station to being served by a target base station, determining whether the source base station and the target base station have a wireless network transmission optimization (WNTO) technical capability; and completing transmission of uplink data or downlink data according to each determined WNTO technical capability of the source base station and the target base station, which effectively improves data transmission efficiency in a wireless network.

Abstract: Disclosed are a protocol stack adaptation method and apparatus, where a network transmission optimization technology can be deployed in a wireless network, thereby optimizing a wireless transmission network. The method includes acquiring a first wireless transmission protocol packet, and detecting, by using a first preset detection rule, whether the first wireless transmission protocol packet carries user data. If the first wireless transmission protocol packet carries user data, the method includes adapting the first wireless transmission protocol packet to a corresponding first standard Internet Protocol (IP) data packet; sending the first standard IP data packet to a network transmission optimization (NTO) device; receiving a second standard IP data packet sent by the NTO device; and, adapting the second standard IP data packet to a corresponding second wireless transmission protocol packet.

Abstract: Embodiments of the present invention disclose a data transmission method and a related apparatus, which are used to implement compression of data transmitted on a backhaul to increase throughput of the backhaul. The method in the embodiments of the present invention includes: parsing a received Internet Protocol (IP) data packet to obtain a transmission network protocol header, a transmission tunneling protocol header, a user data protocol header, and user application layer data; compressing the transmission tunneling protocol header, the user data protocol header, and the user application layer data to obtain a compressed transmission network protocol payload; using the transmission network protocol header to encapsulate the compressed transmission network protocol payload to obtain a compressed IP data packet; and sending the compressed IP data packet to a decoding device in a core network or in a base station.

Abstract: Disclosed is a content encoding pre-synchronization method, comprising: a network device selecting a popular index with a high frequency of appearance from all indexes stored by the network device; determining, among base stations under management, another base station that is of the same type as a base station receiving the popular index, and when the link is idle, sending the popular index and data corresponding to the popular index to the base station. In the content encoding pre-synchronization method provided by an embodiment of the present invention, a popular index and a base station to which the index may be sent can be predetermined, and when the link is idle, the popular index is sent to the corresponding base station in advance, thereby reducing the sending delay in busy time, improving the compression ratio in busy time, and avoiding a loss of synchronization data caused by a busy link.

Abstract: Disclosed are a protocol stack adaptation method and apparatus, where a network transmission optimization technology can be deployed in a wireless network, thereby optimizing a wireless transmission network. The method includes acquiring a first wireless transmission protocol packet, and detecting, by using a first preset detection rule, whether the first wireless transmission protocol packet carries user data. If the first wireless transmission protocol packet carries user data, the method includes adapting the first wireless transmission protocol packet to a corresponding first standard Internet Protocol (IP) data packet; sending the first standard IP data packet to a network transmission optimization (NTO) device; receiving a second standard IP data packet sent by the NTO device; and, adapting the second standard IP data packet to a corresponding second wireless transmission protocol packet.

Abstract: Embodiments of the present invention relate to the communications field, and provide a data processing method and apparatus, which can resolve a problem of excessively small capacity of a base station for data transmission, and improve capacity of the base station for data transmission. In one embodiment, a base station obtains a wireless data packet, performs protocol conversion on the wireless data packet to generate a transmission data packet, adapts the transmission data packet to generate a standard data packet, compresses and optimizes the standard data packet to generate compressed data, and adds the compressed data to a preset data packet. The present invention is used for data processing.

Abstract: Embodiments of the present application disclose a data transmission method and system, and a related apparatus. The method in the embodiments of the present application includes: when a network-side data transmission apparatus detects that a terminal is handed over from being served by a source base station to being served by a target base station, determining whether the source base station and the target base station have a wireless network transmission optimization (WNTO) technical capability; and completing transmission of uplink data or downlink data according to each determined WNTO technical capability of the source base station and the target base station, which effectively improves data transmission efficiency in a wireless network.