Patents by Inventor Eng Huat Goh

Eng Huat Goh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11133261
    Abstract: An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Chee Kheong Yoon, Jia Yan Go
  • Patent number: 11114421
    Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
  • Publication number: 20210202441
    Abstract: Various embodiments are generally directed to an electronic assembly comprising at least two dies stacked on top of each other. Metal columns of different heights electrically connect the dies to a system substrate.
    Type: Application
    Filed: February 5, 2016
    Publication date: July 1, 2021
    Applicant: INTEL CORPORATION
    Inventors: ENG HUAT GOH, CHU AUN LIM, UPENDRA R. SHETH, ROBERT STARKSTON
  • Publication number: 20210202380
    Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Inventors: Jiun Hann SIR, Poh Boon KHOO, Eng Huat GOH, Amruthavalli Pallavi ALUR, Debendra MALLIK
  • Publication number: 20210183775
    Abstract: Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.
    Type: Application
    Filed: September 17, 2020
    Publication date: June 17, 2021
    Inventors: Min Suet Lim, Eng Huat Goh, MD Altaf Hossain
  • Patent number: 10998262
    Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh, Amruthavalli Pallavi Alur, Debendra Mallik
  • Publication number: 20210098352
    Abstract: A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.
    Type: Application
    Filed: June 25, 2020
    Publication date: April 1, 2021
    Inventors: Jiun Hann Sir, Eng Huat Goh, Poh Boon Khoo
  • Publication number: 20210100101
    Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.
    Type: Application
    Filed: June 17, 2020
    Publication date: April 1, 2021
    Inventors: Chee How Lim, Eng Huat Goh, Jon Sern Lim, Khai Ern See, Min Suet Lim, Tin Poay Chuah, Yew San Lim
  • Patent number: 10943864
    Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, J-Wing Teh, Bok Eng Cheah
  • Publication number: 20210057318
    Abstract: Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate.
    Type: Application
    Filed: June 25, 2020
    Publication date: February 25, 2021
    Inventors: Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh
  • Patent number: 10923415
    Abstract: Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Shawna M. Liff, Feras Eid
  • Publication number: 20210035738
    Abstract: Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.
    Type: Application
    Filed: July 2, 2016
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim
  • Publication number: 20210035880
    Abstract: Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion.
    Type: Application
    Filed: July 2, 2016
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Xi Guo
  • Publication number: 20200411438
    Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 31, 2020
    Inventors: Boon Ping Koh, Eng Huat Goh, Jiun Hann Sir, Khang Choong Yong, Min Suet Lim, Wil Choon Song
  • Publication number: 20200411448
    Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a package substrate on a substrate, a die on the package substrate, and a conductive stiffener over the package substrate and the substrate. The conductive stiffener surrounds the package substrate, where the conductive stiffener has a top portion and a plurality of sidewalls, and where the top portion is directly disposed on the package substrate, and the sidewalls are vertically disposed on the substrate. The semiconductor package also includes the substrate that has a plurality of conductive pads, where the conductive pads are conductively coupled to a ground source. The conductive stiffener may conductively couple the package substrate to the conductive pads of the substrate. The top portion may have a cavity that surrounds the die, where the top portion is directly disposed on a plurality of outer edges of the package substrate.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Eng Huat GOH, Jiun Hann SIR, Min Suet LIM, Khang Choong YONG, Boon Ping KOH, Wil Choon SONG
  • Publication number: 20200404787
    Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Inventors: Chee Ling Wong, Wil Choon Song, Khang Choong Yong, Eng Huat Goh, Mohd Muhaiyiddin Bin Abdullah, Tin Poay Chuah
  • Patent number: 10861839
    Abstract: Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Hoay Tien Teoh
  • Patent number: 10856454
    Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Yew San Lim, Jia Yan Go, Tin Poay Chuah, Eng Huat Goh
  • Publication number: 20200357744
    Abstract: Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Khang Choong YONG, Eng Huat GOH, Min Suet LIM, Robert SANKMAN, Telesphor KAMGAING, Wil Choon SONG, Boon Ping KOH
  • Publication number: 20200328151
    Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 15, 2020
    Inventors: Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh, Amruthavalli Pallavi Alur, Debendra Mallik