Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.

Abstract: A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.

Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

Abstract: A semiconductor package substrate has a cavity on the land side among the ball-grid array, and a support structure inserted into the cavity as well as covering at least one device that is seated on the land side. The cavity is an enclave or an exclave. The support structure takes on several useful compositions as well as shapes and sizes.

Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.

Abstract: Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.

Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.

Abstract: Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

Abstract: An electronic device comprises an air core inductor including an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.

Abstract: The electronic assembly includes a printed circuit board; an electronic package that includes an electronic component mounted on a substrate, wherein the substrate is mounted to the printed circuit board; a first memory module mounted to the printed circuit board such that the first memory module is adjacent to the electronic package; a second memory module mounted to the printed circuit board; and a substrate bridge that electrically connects the first and second memory modules to the electronic package, wherein a lower surface of the substrate bridge is connected to an upper surface of the substrate and an upper surface of the first and second memory modules.

Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.

Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

Abstract: Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.

Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.