Abstract: A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.

Abstract: An apparatus includes a first die attach pad and a second die attach pad. A first die is attached to the first die attach pad and a second die is attached to the second die attach pad. The first die attach pad and the second die attach pad are separated by a gap. A first edge of the first die attach pad adjacent to the gap is thinner than a second edge of the first die attach pad. The first edge of the first die attach pad is opposite the second edge of the first die attach pad. A first edge of the second die attach pad adjacent to the gap is thinner than a second edge of the second die attach pad. The first edge of the second die attach pad is opposite the second edge of the second die attach pad.

Abstract: An electronic device includes a substrate, a dielectric spacer, a semiconductor die, and a package structure. The substrate has a dielectric layer, a die pad, first and second leads, a conductive via, and a conductive trace, the dielectric layer has an opening extending into a side, the die pad is coupled to the first lead, the second lead is coupled to the conductive via, and the conductive trace is coupled to the via. The dielectric spacer is mounted above the die pad in the opening, and the semiconductor die is mounted above the dielectric spacer, the semiconductor die includes a temperature sensor, and an electrical connection couples the semiconductor die to the conductive trace. The package structure extends on the side of the dielectric layer, on the semiconductor die, and on the conductive trace, the package structure extending around the dielectric spacer and to the die pad in the opening.

Abstract: In a described example, an apparatus includes: a semiconductor die having bond pads on a device side surface, the semiconductor die having a ground plane spaced from the bond pads by a spacing distance. The bond pads have an upper surface for receiving a ball bond, and an outer boundary, the bond pads having vertical sides extending from the upper surface to a bottom surface, the bottom surface formed over the device side surface of the semiconductor die. A protective overcoat (PO) is formed overlying the ground plane and overlying the vertical sides of the bond pads, and overlying a portion of the upper surface of the bond pads, and having an opening exposing the remaining portion of the upper surface of the bond pads, the protective overcoat having a dielectric constant of less than 3.8.

Abstract: An assembly including an electrical connection substrate formed of material having a Young's modulus of less than about 10 MPa, an acoustic device die having opposite end portions mounted on and electrically connected to the electrical connection substrate and a mold compound layer encapsulating the acoustic device die and interfacing with the substrate.

Abstract: An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, and a multilayer dielectric between the sacrificial fuse element and the semiconductor substrate, the multilayer dielectric forming one or more planar gaps beneath a profile of the sacrificial fuse element.

Abstract: An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

Abstract: In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.

Abstract: A magnetic assembly includes a multilevel lamination or metallization structure with a core dielectric layer, dielectric stack layers, a high permittivity dielectric layer, and first and second patterned conductive features, the dielectric stack layers having a first relative permittivity, the high permittivity dielectric layer extends between and contacting the first patterned conductive feature and one of the dielectric stack layers or the core dielectric layer, the high permittivity dielectric layer has a second relative permittivity, and the second relative permittivity is at least 1.5 times the first relative permittivity to mitigate dielectric breakdown in isolation products.

Abstract: An electronic device has a fuse circuit including a semiconductor die and first and second bond wires, the semiconductor die having a bond pad and a fuse, the fuse having first and second portions, the bond pad coupled to the first portion of the fuse, and the second portion of the fuse coupled to a protected circuit, the first bond wire having a first end coupled to the bond pad and a second end coupled to a conductive terminal, and the second bond wire having a first end coupled to the second end of the first bond wire and a second end coupled to the conductive terminal.

Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.

Abstract: An electronic device includes a substrate, a dielectric spacer, a semiconductor die, and a package structure. The substrate has a dielectric layer, a die pad, first and second leads, a conductive via, and a conductive trace, the dielectric layer has an opening extending into a side, the die pad is coupled to the first lead, the second lead is coupled to the conductive via, and the conductive trace is coupled to the via. The dielectric spacer is mounted above the die pad in the opening, and the semiconductor die is mounted above the dielectric spacer, the semiconductor die includes a temperature sensor, and an electrical connection couples the semiconductor die to the conductive trace. The package structure extends on the side of the dielectric layer, on the semiconductor die, and on the conductive trace, the package structure extending around the dielectric spacer and to the die pad in the opening.

Abstract: In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.

Abstract: In a described example, an apparatus includes: a semiconductor die having bond pads on a device side surface, the semiconductor die having a ground plane spaced from the bond pads by a spacing distance. The bond pads have an upper surface for receiving a ball bond, and an outer boundary, the bond pads having vertical sides extending from the upper surface to a bottom surface, the bottom surface formed over the device side surface of the semiconductor die. A protective overcoat (PO) is formed overlying the ground plane and overlying the vertical sides of the bond pads, and overlying a portion of the upper surface of the bond pads, and having an opening exposing the remaining portion of the upper surface of the bond pads, the protective overcoat having a dielectric constant of less than 3.8.

Abstract: In a described example, an apparatus includes a transformer including: an isolation dielectric layer with a first surface and a second surface opposite the first surface; a first inductor formed over the first surface, the first inductor comprising a first layer of ferrite material, and a first coil at least partially covered by the first layer of ferrite material; and a second inductor formed over the second surface, the second inductor comprising a second layer of ferrite material and a second coil at least partially covered by the second layer of ferrite material.

Abstract: A method includes placing a semiconductor device package in a test handler, the semiconductor device package having leads of a first portion of a package substrate extending from a mold compound and leads of a second portion isolated from the first portion extending from the mold compound; contacting the first portion with a first and a second conductive slug; contacting the second portion with a third and a fourth conductive slug; contacting a first surface of the mold compound with a first plunger having a conductive plate and an insulating tip; contacting an opposite second surface of the mold compound with a second plunger having a conductive plate and an insulating tip; and placing a high voltage on the first conductive slug while placing approximately half the high voltage on the conductive plate of the first plunger, and placing a ground voltage on the third conductive slug.

Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.

Abstract: In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.