Patents by Inventor Enis Tuncer
Enis Tuncer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11573203Abstract: In a described example, an apparatus includes: at least one electrode having a base on a first surface of a substrate and extending away from the base to an end; a counter-electrode spaced from the end of the at least one electrode, having a first conductive surface facing the end; and a package having a cavity containing the at least one electrode, the substrate, and the counter-electrode, the package having at least one opening configured to allow an atmosphere to enter the cavity.Type: GrantFiled: September 21, 2020Date of Patent: February 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Enis Tuncer
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Patent number: 11569396Abstract: An optical sensor package includes an IC die including a light sensor element, an output node, and bond pads including a bond pad coupled to the output node. A leadframe includes a plurality of leads or lead terminals, wherein at least some of the plurality of leads or lead terminals are coupled to the bond pads including to the bond pad coupled to the output node. A mold compound provides encapsulation for the optical sensor package including for the light sensor element. The mold compound includes a polymer-base material having filler particles including at least one of infrared or terahertz transparent particle composition provided in a sufficient concentration so that the mold compound is optically transparent for providing an optical transparency of at least 50% for a minimum mold thickness of 500 ?m in a portion of at least one of an infrared frequency range and a terahertz frequency range.Type: GrantFiled: November 4, 2020Date of Patent: January 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Enis Tuncer
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Patent number: 11569153Abstract: A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.Type: GrantFiled: March 16, 2020Date of Patent: January 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Enis Tuncer, John Paul Tellkamp
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Publication number: 20230014718Abstract: A semiconductor package includes a first set of leads, a temperature sensor proximate the first set of leads, a second set of leads, a semiconductor die, a first electrical connection between the temperature sensor and the semiconductor die, a second electrical connection between the semiconductor die and the second set of leads, and mold compound at least partially covering the temperature sensor, the semiconductor die, the first set of leads and the second set of leads. The mold compound physically separates the semiconductor die from the temperature sensor and the first set of leads.Type: ApplicationFiled: July 14, 2021Publication date: January 19, 2023Inventor: Enis Tuncer
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Patent number: 11557722Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: GrantFiled: January 6, 2021Date of Patent: January 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Patent number: 11552013Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, and leads spaced from the die pad; a semiconductor die mounted on the die pad; a fuse mounted to a lead, the fuse having a fuse element coupled between a fuse cap and the lead, the fuse having a fuse body with an opening surrounding the fuse element, the fuse cap attached to the fuse body; electrical connections coupling the semiconductor die to the fuse; and mold compound covering the semiconductor die, the fuse, the electrical connections, and a portion of the package substrate, with portions of the leads exposed from the mold compound to form terminals.Type: GrantFiled: March 31, 2021Date of Patent: January 10, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Enis Tuncer
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Patent number: 11538738Abstract: In a described example, an apparatus includes: a package substrate including a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead and a third lead; and a semiconductor die including a temperature sensor mounted on the die pad. The semiconductor die includes a first metallization layer being a metallization layer closest to the active surface of the semiconductor die, and successive metallization layers overlying the previous metallization layer, the metallization layers including a respective conductor layer in a dielectric material for the particular metallization layer and conductive vias; and the temperature sensor formed of the conductor layer in an uppermost metallization layer and coupled to the second lead and to the third lead. The semiconductor die includes a high voltage ring formed in the uppermost metallization layer, spaced from and surrounding the temperature sensor.Type: GrantFiled: July 31, 2021Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Enis Tuncer
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Publication number: 20220384370Abstract: An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.Type: ApplicationFiled: May 26, 2021Publication date: December 1, 2022Applicant: Texas Instruments IncorporatedInventor: Enis Tuncer
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Publication number: 20220352054Abstract: In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.Type: ApplicationFiled: April 30, 2021Publication date: November 3, 2022Inventor: Enis TUNCER
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Publication number: 20220319988Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, and leads spaced from the die pad; a semiconductor die mounted on the die pad; a fuse mounted to a lead, the fuse having a fuse element coupled between a fuse cap and the lead, the fuse having a fuse body with an opening surrounding the fuse element, the fuse cap attached to the fuse body; electrical connections coupling the semiconductor die to the fuse; and mold compound covering the semiconductor die, the fuse, the electrical connections, and a portion of the package substrate, with portions of the leads exposed from the mold compound to form terminals.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventor: Enis Tuncer
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Publication number: 20220319966Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventor: Enis Tuncer
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Publication number: 20220208676Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, and a multilayer dielectric between the sacrificial fuse element and the semiconductor substrate, the multilayer dielectric forming one or more planar gaps beneath a profile of the sacrificial fuse element.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Enis Tuncer, Alejandro Hernandez-Luna
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Publication number: 20220208699Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventor: Enis Tuncer
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Patent number: 11342251Abstract: A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.Type: GrantFiled: September 8, 2020Date of Patent: May 24, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Enis Tuncer
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Publication number: 20220140154Abstract: An optical sensor package includes an IC die including a light sensor element, an output node, and bond pads including a bond pad coupled to the output node. A leadframe includes a plurality of leads or lead terminals, wherein at least some of the plurality of leads or lead terminals are coupled to the bond pads including to the bond pad coupled to the output node. A mold compound provides encapsulation for the optical sensor package including for the light sensor element. The mold compound includes a polymer-base material having filler particles including at least one of infrared or terahertz transparent particle composition provided in a sufficient concentration so that the mold compound is optically transparent for providing an optical transparency of at least 50% for a minimum mold thickness of 500 ?m in a portion of at least one of an infrared frequency range and a terahertz frequency range.Type: ApplicationFiled: November 4, 2020Publication date: May 5, 2022Inventor: Enis Tuncer
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Patent number: 11322433Abstract: In some examples, a package comprises first and second terminals and a conductive pathway coupling the first and second terminals. The conductive pathway is configured to generate a magnetic field. The package comprises a conductive member aligned with and coupled to the conductive pathway. The conductive pathway and the conductive member have a common shape. The package also comprises an insulative layer coupled to the conductive member and a die coupled to the insulative layer and having a circuit configured to measure the magnetic field. The circuit faces the conductive pathway.Type: GrantFiled: April 7, 2020Date of Patent: May 3, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Enis Tuncer, Alejandro Hernandez-Luna
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Publication number: 20220108896Abstract: A method of manufacturing a semiconductor package includes covering a semiconductor die and a plurality of conductive terminals coupled to the semiconductor die in a mold compound, positioning the mold compound between a first pair of electrodes and a second pair of electrodes, and moving a movable electrode of the first pair and a movable electrode of the second pair into a first clamping position. In the first clamping position, each of the first pair of electrodes and the second pair of electrodes electrically couples to a unique subset of the plurality of conductive terminals. The method also includes applying, by the first pair of electrodes, a first voltage to the semiconductor die within the mold compound; and applying, by the second pair of electrodes, a second voltage to the semiconductor die within the mold compound. The second voltage is less than the first voltage.Type: ApplicationFiled: December 14, 2021Publication date: April 7, 2022Inventors: Enis TUNCER, Byron Harry GIBBS
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Publication number: 20220091067Abstract: In a described example, an apparatus includes: at least one electrode having a base on a first surface of a substrate and extending away from the base to an end; a counter-electrode spaced from the end of the at least one electrode, having a first conductive surface facing the end; and a package having a cavity containing the at least one electrode, the substrate, and the counter-electrode, the package having at least one opening configured to allow an atmosphere to enter the cavity.Type: ApplicationFiled: September 21, 2020Publication date: March 24, 2022Inventor: Enis Tuncer
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Patent number: 11201065Abstract: A method of manufacturing a semiconductor package includes covering a semiconductor die and a plurality of conductive terminals coupled to the semiconductor die in a mold compound, positioning the mold compound between a first pair of electrodes and a second pair of electrodes, and moving a movable electrode of the first pair and a movable electrode of the second pair into a first clamping position. In the first clamping position, each of the first pair of electrodes and the second pair of electrodes electrically couples to a unique subset of the plurality of conductive terminals. The method also includes applying, by the first pair of electrodes, a first voltage to the semiconductor die within the mold compound; and applying, by the second pair of electrodes, a second voltage to the semiconductor die within the mold compound. The second voltage is less than the first voltage.Type: GrantFiled: February 14, 2020Date of Patent: December 14, 2021Assignee: Texas Instruments IncorporatedInventors: Enis Tuncer, Byron Harry Gibbs
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Publication number: 20210313258Abstract: In some examples, a package comprises first and second terminals and a conductive pathway coupling the first and second terminals. The conductive pathway is configured to generate a magnetic field. The package comprises a conductive member aligned with and coupled to the conductive pathway. The conductive pathway and the conductive member have a common shape. The package also comprises an insulative layer coupled to the conductive member and a die coupled to the insulative layer and having a circuit configured to measure the magnetic field. The circuit faces the conductive pathway.Type: ApplicationFiled: April 7, 2020Publication date: October 7, 2021Inventors: Enis TUNCER, Alejandro HERNANDEZ-LUNA