Abstract: A method and apparatus for initializing an RRAM and an electronic device are provided. The method includes: inputting a plurality of pulses of a first voltage into an RRAM until memory cells in the RRAM transition from a high resistance state to a low resistance state; inputting a plurality of pulses of a second voltage, a third voltage . . . and an Nth voltage into the RRAM, so that resistance values of the memory cells reach a corresponding preset value, respectively. Voltage values of the first voltage to the Nth voltage gradually decrease. When a total number of input pulses of an ith voltage is greater than a second preset threshold and a resistance change rate is less than a rate threshold, a plurality of pulses of an increased ith voltage are input into the RRAM until the resistance values of the memory cells reach an ith preset value.

Abstract: The disclosure discloses a data writing operation method and device of a resistive random access memory, and the method includes: applying a first pulse voltage to the resistive random access memory, and adding one to a corresponding number to obtain a first number; if the current first number is greater than a first set upper limit value and a current second number is smaller than or equal to a second set upper limit value, obtaining a test value; if the test value does not satisfy a preset condition, applying a second pulse voltage to the resistive random access memory, and adding one to the corresponding number to obtain a second number until the test value satisfies the preset condition or the current second number is greater than the second set upper limit value, thereby improving the writing efficiency.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments, with the first active fragments and the second active fragments parallel and separately extended along a first direction. A plurality of first openings disposed in the substrate, between two adjacent ones of the first active fragments, and a plurality of second openings disposed in the substrate, between two adjacent ones of the second active fragments, wherein an aperture of the second openings is greater than an aperture of the first openings. The shallow trench isolation is disposed in the substrate to fill in the first openings and the second openings, and to surround the active structure.

Abstract: A semiconductor structure, a fabricating method thereof and a semiconductor device, the structure includes a substrate having a STI region and an AA, with an upper surface of the STI region lower than an upper surface of the AA; a stacked covered on the substrate; a first insulating layer covered the stacked structure, a second insulating layer covered the first insulating layer, and a third insulating layer covered the second insulating layer, over the STI region; a first insulating layer covered the stacked structure, over the AA, with an upper surface of the first insulating layer coplanar with an upper surface of the third insulating layer. The structure provides a semiconductor structure having a flat upper surface, avoiding polishing the first insulating layer over the AA to level with the first insulating layer over the STI region, greatly increasing the leakage risk, and reducing working stability of semiconductor devices.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.