Method of fabricating semiconductor memory having a second active region disposed at an outer side of a first active region
The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.
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This application is a division of U.S. application Ser. No. 17/336,275, filed on Jun. 1, 2021. The content of the application is incorporated herein by reference.
BACKGROUND OF THE INVENTION 1. Field of the InventionThe present disclosure generally relates to a semiconductor memory device and a method of fabricating the same, and more particularly, to a semiconductor memory device having active regions and shallow trench isolations and a method of fabricating the same.
2. Description of the Prior ArtWith the miniaturization of semiconductor devices and the complexity of integrated circuits, the size of elements is continuously shrinking and the structure is constantly changing. Therefore, maintaining the performance of small-sized semiconductor elements is the standard purpose of the present industry. In the semiconductor fabricating process, most of the active areas (AAs) are defined on the substrate as a bass element, and then, the required elements are further formed on the AAs. Generally, the AAs are plural patterns formed within the substrate through the photolithography and etching processes. However, due to the sized-shrinking requirements, the width of the AAs has been gradually reduced, and the pitch between the AAs has also been gradually reduced thereby, so that, the fabricating process of AAs encounters plenty limitations and challenges that fails to meet the practical product requirements.
SUMMARY OF THE INVENTIONOne of the objectives of the present disclosure provides a semiconductor memory device and a fabricating method thereof, in which the semiconductor memory device includes an active structure having a second active region disposed around an outer side of a first active region, wherein the second active region further includes a plurality of openings disposed thereon with the locations of the openings being in alignment with particular bit lines and contacts disposed on the particular bit lines, respectively. Accordingly, it is sufficient to avoid the directly connection between the bit lines and the word lines, and the semiconductor memory device may achieve better element performance.
To achieve the purpose described above, one embodiment of the present disclosure provides a semiconductor memory device including a substrate, an active structure and a shallow trench isolation. The active structure is disposed in the substrate, and includes a first active region and a second active region, the first active region includes a plurality of active region units parallel with each other and extending along a first direction, and the second active region is disposed at an outer side of the first active region. The second active region includes a first edge extending along a second direction and a second edge extending along a third direction, and the first edge and the second edge directly connected to a portion of the active region units, wherein the second active region comprises a plurality of first openings, and the first openings are disposed on the second edge. The shallow trench isolation is disposed in the substrate to surround the active structure.
To achieve the purpose described above, one embodiment of the present disclosure provides a method of fabricating a semiconductor memory device including the following steps. Firstly, a substrate is provided, and an active structure is formed in the substrate, wherein the active structure includes a first active region and a second active region, the first active region includes a plurality of active region units parallel with each other and extending along a first direction, and the second active region is disposed at an outer side of the first active region. The second active region includes a first edge extending along a second direction and a second edge extending along a third direction, and the first edge and the second edge directly connected to a portion of the active region units, wherein the second active region further includes a plurality of first openings disposed on the second edge. Then, a shallow trench isolation is formed in the substrate to surround the active structure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
To provide a better understanding of the presented disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are illustrated in the accompanying drawings with numbered elements. In addition, the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure.
Please refer to
As shown in
On the other hand, the second active region 133 is disposed around an outer side of the first active region 131. In the present embodiment, the second active region 133 further includes at least a first edge 133a extended along the second direction D2, and at least two second edges 133b extended along the third direction D3. Each of the two second edge 133b is opposite to one another, and adjacent to the first edge 133a, such that, the whole second active region 133 may therefore perform like a rectangular frame (not shown in the drawings) to directly in contact with a portion of active region units 131a. In other words, while disposing the second active region 133, a portion of the active region units 131a may be further connected to the first edge 133a and the second edge 133b of the second active region 133, and another portion of the active region units 131a may be spaced apart from the first edge 133a and the second edge 133b of the second active region 133, as shown in
It is noted that, the second active region 133 further includes a plurality of first openings 132 and a plurality of second openings 134 which are respectively disposed on the second edges 133b at two opposite sides. Namely, the first openings are sequentially arranged on the second edge 133b and the second openings are sequentially arranged on the another second edge 133b, as shown in
Next, a plurality of gate structures, preferably being buried gate structures 140, is formed in the substrate 110, as shown in
Following these, at least a bit line (BL) 160 is formed on the substrate 110, and at least a contact 170 is formed on the at least a bit line 160 and at least a contact 190 is formed on the word line (namely, the buried gate structure 140), to respectively electrically connect to the at least a bit line 160 or the word lines (namely, the buried gate structure 140). As shown in
It is noteworthy that, each of the bit lines 160 crosses over the active structure 130, to partially overlap with the first active region 131 and the second active region 133 underneath, wherein a portion of the bit lines 161 partially overlap with the second edge 133b at one side (such as the left side of the bit lines 161 as shown in
According to above arrangements, the semiconductor memory device 100 of the first preferable embodiment is achieved. The semiconductor memory device 100 includes the second active region 133 around at the outer side of the first active region 131, with a portion of the active region units 131a further connecting to the first edge 133a and the second edges 133b of the second active region 133 to uniformly disperse the stress suffered from the active region units 131a and the shallow trench isolation 120, thereby obtaining a relative reliable structure. Moreover, the first openings 132 and the second openings 134 are further disposed on the second active region 130, with the locations of the first openings 132 being in alignment with the bit lines 163 and the contacts 173 in the second direction D2, respectively, and with the locations of the second openings 134 being in alignment with the bit lines 161 and the contacts 171 in the second direction D2, respectively, thereby avoiding the direct connection of the bit lines 160 and the word lines (namely, the buried gate structure 140). In this way, the semiconductor memory device 100 of the present embodiment may therefore achieve an improved performance.
However, people in the art should fully realize that the semiconductor memory device and the fabricating method thereof are not be limited to aforementioned embodiment and may include other examples or may be achieved through other strategies to meet practical product requirements. For example, in one embodiment, the etching conditions may be further adjusted during the patterning process of the second active region 133 to form the active structure with rounding corners, but not limited thereto. Also, in another embodiment as shown in
Please refer to
Precisely speaking, the first openings 232 are sequentially disposed on one of the second edges 133b of the second active region 133, and the second openings 234 are sequentially disposed on another one of the second edges 133b of the second active region 133, as shown in
With these arrangements, the locations of the first openings 232 may also be in alignment with the bit lines 163 and the contacts 173 respectively, in the second direction D2, and the locations of the second openings 234 may be in alignment with the bit lines 161 and the contacts 171 respectively, in the second direction D2, to prevent from the directly connection between the bit lines 160 and the word lines (namely, the buried gate structures 140). Then, the semiconductor memory device 200 of the second preferable embodiment of the present disclosure may also achieve an improved performance.
Please refer to
Precisely speaking, the third edge 333c is for example disposed between the first edge 133a extending along the second direction D2 and the second edge 133b extending along the third direction D3, that is, the first edge 133a is adjacent to the third edge 333c, and the third edge 333c is adjacent to the second edge 133b, thereby making the second active region 133 to present like a polygon frame (not shown in the drawings) around the first active region 131. In the present embodiment, the third edge 333c for example includes a maximum width T1 which is the same as that of the first edge 133a and the second edge 133b, but is not limited thereto. In another embodiment, the third edge 333c may also include a relative greater width (not shown in the drawings), for example being greater than the maximum width T1 of the first edge 133a and the second edge 133b. People in the art should easily realize that the extending direction, as well as the practical disposing number, of the third edges may be adjustable due to product requirements, and the second active region may therefore present various shape and which is not limited to the aforementioned shape.
According to above arrangements, the second active region 133 may obtain a relative stable and strengthened structure through disposing the third edge 333c, so as to improve the stresses around the semiconductor memory device 300, thereby avoiding the structural collapse or damages. Meanwhile, the first openings 132 disposed on the second active region 133 is also in alignment with the bit lines 163 and the contacts 173 respectively, in the second direction D2, and the second openings 134 disposed on the second active region 133 is also in alignment with the bit lines 161 and the contacts 171 respectively, in the second direction D2, to prevent from the direct connection between the bit lines 160 and the word lines (namely the buried gate structures 140). In this way, the semiconductor memory device 300 of the third preferable embodiment of the present disclosure may also achieve an improved performance.
Please refer to
Precisely speaking, the third edge 433c for example extends along the first direction D1, between the first edge 133a and the second edge 133b, so that, the second active region 133 may entirely present like a polygon frame (not shown in the drawings) around the first active region 131. The protruding portions 435 and the third edge 433c may be monolithic, and which is disposed at one side of the third edge 433c which is away from the first active region 131. Namely, the protruding portion 435 further extends outwardly into the second region 103, for example along a fourth direction D4 which is different from the first direction D1, the second direction D2 and the third direction D3, thereby additionally enhancing the structural strength outside the second active region 133.
According to above arrangements, the second active region 133 may obtain an enhanced structural strength through disposing the third edge 433c and the protruding portion s 435, so as to improve the stresses around the semiconductor memory device 400, thereby avoiding the structural collapse or damages. Also, people in the art should easily understand that the practical number, the shape and the size of the protruding portions may all be adjustable due to product requirements, and which are not limited to what is shown in
Overall speaking, according to the semiconductor memory device in the present disclosure, a second active region disposed around the first active region is disposed at the periphery of the device, and the openings are further disposed on the second active region. The locations of the openings is in alignment with particular bit lines and the contacts disposed on the particular bit lines, respectively, so that, it is sufficient to avoid the directly conduction between the bit lines and the word lines, to provide improved performance to the semiconductor memory device. Also, the second active region further includes the strengthened structure, such as the edges with relative greater thickness or the protruding portions, and the periphery of the device may therefore obtain a relative stable, strengthened structure to protect the elements disposed inside the device. Then, the semiconductor memory device of the present disclosure may achieve an improved performance.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A method of forming a semiconductor memory device, comprising;
- providing a substrate;
- forming an active structure in the substrate, the active structure comprising: a first active region comprising a plurality of active region units parallel with each other and extending along a first direction; and a second active region disposed at an outer side of the first active region, the second active region comprising a first edge extending along a second direction and a second edge extending along a third direction, and the first edge and the second edge directly connected to a portion of the active region units, wherein the second active region comprises a plurality of first openings, and the first openings are disposed on the second edge; and
- forming a shallow trench isolation in the substrate, the shallow trench isolation surrounding the active structure.
2. The method of forming the semiconductor memory device accordingly to claim 1, further comprising:
- forming at least a bit line on the substrate, the at least a bit line extending along the second direction to intersect the active region units, wherein the second direction is perpendicular to the third direction and is not perpendicular to the first direction; and
- forming at least a contact on the at least a bit line to electrically connect the at least a bit line.
3. The method of forming the semiconductor memory device accordingly to claim 2, wherein the first edge of the second active region is parallel with the at least a bit line.
4. The method of forming the semiconductor memory device accordingly to claim 2, wherein the at least a bit line comprises a plurality of first bit lines and a plurality of second bit lines, the at least a contact comprises a plurality of first contacts and a plurality of second contacts, the first bit lines and the second bit lines are alternately arranged along the third direction, the first contacts are disposed on first ends of the first bit lines respectively, and the second contacts are disposed on second ends of the second bit lines respectively.
5. The method of forming the semiconductor memory device accordingly to claim 4, wherein each of the first openings is disposed between any two of the first contacts, and the first openings are in alignment with the second contacts.
6. The method of forming the semiconductor memory device accordingly to claim 4, wherein the second active region further comprises a plurality of second openings disposed on another second edge, wherein the another second edge extends along the third direction and is opposite to the second edge, and each of the second openings is disposed between any two of the second contacts.
7. The method of forming the semiconductor memory device accordingly to claim 6, wherein the second openings are in alignment with the first contacts.
8. The method of forming the semiconductor memory device accordingly to claim 1, further comprising:
- forming at least a third edge between the first edge and the second edge, and the third edge extending along the first direction.
9. The method of forming the semiconductor memory device accordingly to claim 8, further comprising:
- forming a plurality of protruding portions on the at least a third edge, the protruding portions extending along a fourth direction which is different from the first direction, the second direction and the third direction.
10. The method of forming the semiconductor memory device accordingly to claim 8, wherein a maximum width of the third edge is equal to a maximum width of the second edge or a maximum width of the first edge.
11. The method of forming the semiconductor memory device accordingly to claim 8, wherein a maximum width of the third edge is greater than a maximum width of the second edge, a maximum width of the first edge, or a maximum width of the active region units.
12. The method of forming the semiconductor memory device accordingly to claim 11, wherein the maximum width of the active region units is smaller than the maximum width of the first edge or the maximum width of the second edge.
13. The method of forming the semiconductor memory device accordingly to claim 1, further comprising:
- forming a plurality of word lines in the substrate, each of the word lines extended parallel with the second edge of the second active region.
14. The method of forming the semiconductor memory device accordingly to claim 13, wherein each of the word lines intersects with the first edge of the second active region and the active region units.
15. The method of forming the semiconductor memory device accordingly to claim 13, further comprising:
- a plurality of third contacts disposed on one ends of the word lines respectively.
9704816 | July 11, 2017 | Huang |
20160233297 | August 11, 2016 | Tomoyama |
112133699 | December 2020 | CN |
2021153266 | August 2021 | WO |
- The specification, including the claims, and drawings in the CN application No. CN202022661807.3 , Filing Date: Nov. 17, 2020.
- Huang, the specification, including the claims, and drawings in the U.S. Appl. No. 15/296,942 , Filing Date: Oct. 18, 2016.
Type: Grant
Filed: Jul 5, 2022
Date of Patent: Jul 18, 2023
Patent Publication Number: 20220359527
Assignee: Fujian Jinhua Integrated Circuit Co., Ltd. (Quanzhou)
Inventors: Janbo Zhang (Quanzhou), Enping Cheng (Quanzhou), Li-Wei Feng (Quanzhou), Yu-Cheng Tung (Quanzhou)
Primary Examiner: Hoai V Pham
Application Number: 17/858,055
International Classification: H10B 12/00 (20230101);