Patents by Inventor Enrique Q. Garcia
Enrique Q. Garcia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11892971Abstract: A method is disclosed for maintaining a current operating state of an enclosure when a controller card of the enclosure is repaired and/or replaced. In one embodiment, such a method maintains, within a controller card of an enclosure, operating parameters used to establish an operating state of the enclosure. The method further offloads, from the controller card while the controller card is installed in the enclosure, the operating parameters to a location external to the controller card. Upon removal of the controller card from the enclosure, the method maintains the operating state of the enclosure using the operating parameters stored in the external location. Upon reinstalling the controller card in the enclosure, the method optionally retrieves the operating parameters from the external location and initializes the controller card with the operating parameters. A corresponding system and computer program product are also disclosed.Type: GrantFiled: March 1, 2019Date of Patent: February 6, 2024Assignee: International Business Machines CorporationInventors: John C. Elliott, Gary W. Batchelor, Enrique Q. Garcia, Ronald D. Martens, Todd C. Sorenson
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Patent number: 10956148Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: GrantFiled: November 14, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Patent number: 10956354Abstract: Provided are techniques for detecting a type of storage adapter connected to an Input/Output (I/O) bay and miscabling of a microbay housing the storage adapter. Under control of an Input/Ouput (I/O) bay, cable sidebands are driven high for a predetermined period of time. It is determined whether a cable sidebands response has been detected that indicates that the cable sidebands have been driven low. In response to determining that the cable sidebands response has been detected, it is determined that the I/O bay is connected to a first storage adapter supporting a first protocol for the cable sidebands. In response to determining that the cable sidebands response has not been detected, it is determined that the I/O bay is connected to a second storage adapter supporting a second protocol for the cable sidebands. Moreover, I/O bay and port numbers stored by the microbay are used to determine miscabling.Type: GrantFiled: February 25, 2019Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Gary W. Batchelor, Enrique Q. Garcia, Jay T. Kirch, Trung N. Nguyen, Todd C Sorenson
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Patent number: 10833979Abstract: In accordance with one aspect of the present description, a node of the distributed computing system has multiple communication paths to a data processing resource lock which controls access to shared resources, for example. In this manner, at least one redundant communication path is provided between a node and a data processing resource lock to facilitate reliable transmission of data processing resource lock signals between the node and the data processing resource lock. Other features and aspects may be realized, depending upon the particular application.Type: GrantFiled: June 13, 2019Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yolanda Colpo, John C. Elliott, Enrique Q. Garcia, Larry Juarez, Todd C. Sorenson
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Publication number: 20200278946Abstract: A method is disclosed for maintaining a current operating state of an enclosure when a controller card of the enclosure is repaired and/or replaced. In one embodiment, such a method maintains, within a controller card of an enclosure, operating parameters used to establish an operating state of the enclosure. The method further offloads, from the controller card while the controller card is installed in the enclosure, the operating parameters to a location external to the controller card. Upon removal of the controller card from the enclosure, the method maintains the operating state of the enclosure using the operating parameters stored in the external location. Upon reinstalling the controller card in the enclosure, the method optionally retrieves the operating parameters from the external location and initializes the controller card with the operating parameters. A corresponding system and computer program product are also disclosed.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Applicant: International Business Machines CorporationInventors: John C. Elliott, Gary W. Batchelor, Enrique Q. Garcia, Ronald D. Martens, Todd C. Sorenson
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Publication number: 20200081702Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Patent number: 10540170Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: GrantFiled: September 12, 2018Date of Patent: January 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Patent number: 10528412Abstract: In one aspect, multiple data path error collection is provided in a storage management system. In one embodiment, an error condition in a main data path between the storage controller and at least one of a host and a storage unit is detected, and in response, a sequence of error data collection operations to collect error data through a main path is initiated. In response to a failure to collect error data at a level of the sequential error data collection operations, error data is collected through an alternate data path as a function of the error data collection level at which the failure occurred. Other aspects are described.Type: GrantFiled: November 6, 2017Date of Patent: January 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Batchelor, Matthew D. Carson, Enrique Q. Garcia, Larry Juarez, Jay T. Kirch, Tony Leung, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Publication number: 20190332562Abstract: Provided are techniques for detecting a type of storage adapter connected to an Input/Output (I/O) bay and miscabling of a microbay housing the storage adapter. Under control of an Input/Ouput (I/O) bay, cable sidebands are driven high for a predetermined period of time. It is determined whether a cable sidebands response has been detected that indicates that the cable sidebands have been driven low. In response to determining that the cable sidebands response has been detected, it is determined that the I/O bay is connected to a first storage adapter supporting a first protocol for the cable sidebands. In response to determining that the cable sidebands response has not been detected, it is determined that the I/O bay is connected to a second storage adapter supporting a second protocol for the cable sidebands. Moreover, I/O bay and port numbers stored by the microbay are used to determine miscabling.Type: ApplicationFiled: February 25, 2019Publication date: October 31, 2019Inventors: Gary W. Batchelor, Enrique Q. Garcia, Jay T. Kirch, Trung N. Nguyen, Todd C. Sorenson
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Publication number: 20190297006Abstract: In accordance with one aspect of the present description, a node of the distributed computing system has multiple communication paths to a data processing resource lock which controls access to shared resources, for example. In this manner, at least one redundant communication path is provided between a node and a data processing resource lock to facilitate reliable transmission of data processing resource lock signals between the node and the data processing resource lock. Other features and aspects may be realized, depending upon the particular application.Type: ApplicationFiled: June 13, 2019Publication date: September 26, 2019Inventors: Yolanda Colpo, John C. Elliott, Enrique Q. Garcia, Larry Juarez, Todd C. Sorenson
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Patent number: 10374940Abstract: In accordance with one aspect of the present description, a node of the distributed computing system has multiple communication paths to a data processing resource lock which controls access to shared resources, for example. In this manner, at least one redundant communication path is provided between a node and a data processing resource lock to facilitate reliable transmission of data processing resource lock signals between the node and the data processing resource lock. Other features and aspects may be realized, depending upon the particular application.Type: GrantFiled: November 30, 2017Date of Patent: August 6, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yolanda Colpo, John C. Elliott, Enrique Q. Garcia, Larry Juarez, Todd C. Sorenson
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Patent number: 10255223Abstract: Provided are techniques for detecting a type of storage adapter connected to an Input/Output (I/O) bay and miscabling of a microbay housing the storage adapter. Under control of an Input/Ouput (I/O) bay, cable sidebands are driven high for a predetermined period of time. It is determined whether a cable sidebands response has been detected that indicates that the cable sidebands have been driven low. In response to determining that the cable sidebands response has been detected, it is determined that the I/O bay is connected to a first storage adapter supporting a first protocol for the cable sidebands. In response to determining that the cable sidebands response has not been detected, it is determined that the I/O bay is connected to a second storage adapter supporting a second protocol for the cable sidebands. Moreover, I/O bay and port numbers stored by the microbay are used to determine miscabling.Type: GrantFiled: December 5, 2016Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Gary W. Batchelor, Enrique Q. Garcia, Jay T. Kirch, Trung N. Nguyen, Todd C Sorenson
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Publication number: 20190012165Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: ApplicationFiled: September 12, 2018Publication date: January 10, 2019Inventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Patent number: 10114633Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: GrantFiled: December 8, 2016Date of Patent: October 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Publication number: 20180165082Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: ApplicationFiled: December 8, 2016Publication date: June 14, 2018Inventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Publication number: 20180160561Abstract: Provided are techniques for detecting a type of storage adapter connected to an Input/Output (I/O) bay and miscabling of a microbay housing the storage adapter. Under control of an Input/Ouput (I/O) bay, cable sidebands are driven high for a predetermined period of time. It is determined whether a cable sidebands response has been detected that indicates that the cable sidebands have been driven low. In response to determining that the cable sidebands response has been detected, it is determined that the I/O bay is connected to a first storage adapter supporting a first protocol for the cable sidebands. In response to determining that the cable sidebands response has not been detected, it is determined that the I/O bay is connected to a second storage adapter supporting a second protocol for the cable sidebands. Moreover, I/O bay and port numbers stored by the microbay are used to determine miscabling.Type: ApplicationFiled: December 5, 2016Publication date: June 7, 2018Inventors: Gary W. Batchelor, Enrique Q. Garcia, Jay T. Kirch, Trung N. Nguyen, Todd C. Sorenson
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Patent number: 9946628Abstract: Provided are a computer program product, system, and method for embedding and executing trace functions in code to gather trace data. A plurality of trace functions are embedded in the code. For each embedded trace function, a trace level is included indicating code to which the trace applies. The trace level comprises one of a plurality of levels. During the execution of the code, the embedded trace functions having one of the levels associated with a specified at least one level specified are executed. The embedded trace functions associated with at least one level not comprising one of the at least one specified level are not invoked.Type: GrantFiled: April 22, 2016Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herve G. P. Andre, Yolanda Colpo, Enrique Q. Garcia, Mark E. Hack, Larry Juarez, Ricardo S. Padilla, Todd C. Sorenson
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Publication number: 20180102966Abstract: In accordance with one aspect of the present description, a node of the distributed computing system has multiple communication paths to a data processing resource lock which controls access to shared resources, for example. In this manner, at least one redundant communication path is provided between a node and a data processing resource lock to facilitate reliable transmission of data processing resource lock signals between the node and the data processing resource lock. Other features and aspects may be realized, depending upon the particular application.Type: ApplicationFiled: November 30, 2017Publication date: April 12, 2018Inventors: Yolanda Colpo, John C. Elliott, Enrique Q. Garcia, Larry Juarez, Todd C. Sorenson
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Patent number: 9942160Abstract: Efficient logging in a control system is provided. A temporary history record corresponding to a message transaction placed onto a message queue data structure is generated. A total processing time for the received message transaction is determined. The total processing time is compared with a previously determined peak processing time value. In response to determining that the total processing time exceeds the previously determined peak processing time value, the temporary history record corresponding to the received message transaction is stored in an event log.Type: GrantFiled: November 20, 2015Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventor: Enrique Q. Garcia
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Publication number: 20180060158Abstract: In one aspect, multiple data path error collection is provided in a storage management system. In one embodiment, an error condition in a main data path between the storage controller and at least one of a host and a storage unit is detected, and in response, a sequence of error data collection operations to collect error data through a main path is initiated. In response to a failure to collect error data at a level of the sequential error data collection operations, error data is collected through an alternate data path as a function of the error data collection level at which the failure occurred. Other aspects are described.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Inventors: Gary W. Batchelor, Matthew D. Carson, Enrique Q. Garcia, Larry Juarez, Jay T. Kirch, Tony Leung, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson