Abstract: Analog and digital video signals are each representative of a picture and each may carry program guide information. A demultiplexer has the digital video signal as an input and the program guide information as an output. A demodulator has at least a luminance component of the analog video signal as an input and the program guide information as an output. A microprocessor, a video graphics adapter, the demultiplexer and the demodulator are interconnected by a data bus. Either of the program guide outputs is transferable to the video graphics adapter, which formats a graphics video signal representative of the program guide information. The graphics video signal and a selected one of the video signals are inputs to a multiplexer, which outputs a combined video signal representative of both the program guide information and the picture represented by the selected video signal.

Abstract: A data slicer for extracting auxiliary video data from a video signal adapts a data slicing level to the amplitude of the data signal as indicated by the average value of a run-in clock (RIC) signal that is included in the video signal. Control of the slicing level occurs during a window interval that spans an integral number of cycles of the RIC signal. The presence of the RIC signal within the window interval may be verified as part of the slicing level adjustment operation. The data slicer is suitable for implementation in a digital integrated circuit.

Abstract: A video display has a first format display ratio. A mapping circuit maps an adjustable picture display are on the video display. A signal processor generates first and second video signals from input video signals having one of different format display ratios. A switching circuit selectively couples video signal sources as the input video signals. The signal processor can manipulate data from the input video signals by selective interpolation and cropping. A synchronizing circuit synchronizes the first and second signal processors with the mapping circuit. A selecting circuit selects as an output video signal between one of the first and second processed video signals and a combination of the first and second processed video signals. A control circuit controls the mapping circuit, the first and second signal processors and the selecting circuit to adjust in format display ratio and image aspect ratio each picture represented in the output video signal.

Abstract: A television receiver embodying the invention includes a plurality of luminance signal sources, each capacitively coupled to an input of a luminance signal selection switch and each capacitor being coupled to a respective clamp circuit with each clamp circuit having a reference voltage input coupled to a common reference voltage source. A sync separator is provided having a first input coupled to receive the output of luminance signal selection switch and a second input coupled to a source of reference potential derived from said reference voltage source. Advantageously, the overall number of clamp circuits is minimized by merging the sync separator circuit with the input signal selection clamping circuit.

Abstract: An automatic kinescope bias (AKB) arrangement embodied in an integrated circuit (IC) includes circuitry for generating a timing signal during an AKB test interval, circuitry for generating a test signal in response to the timing signal, and circuitry including an output terminal for coupling the test signal to the kinescope. The AKB IC also includes an input terminal and a switching element coupled between the input terminal and the output terminal and responsive to the timing signal for selectively decoupling the input terminal from the output terminal. In a television system which includes a bias network which is coupled to the output of the video signal source and which inhibits the kinescope from being cutoff during the AKB test interval, the input terminal of the AKB IC is coupled to the output terminal of the video signal source. This allows the bias network to be decoupled from the display device during the AKB test interval, thereby preventing the bias network from affecting AKB operation.

Abstract: A signal slicer of a sync separator includes a comparator for generating an output signal in accordance with a difference between a black level restored video signal and a slice level. The slice level is established dynamically, in accordance with the peak level of the sync pulse between the peak of the sync pulse and the black level. When the sync pulse occurs in the video signal, the output signal of the signal slicer assumes an active, first logical state; conversely, between consecutively occurring sync pulses, the output signal assumes an inactive, second logical state. The slice level is clamped to a predetermined level to prevent the occurrence of the first logical state when no video signal is received.

Abstract: An adaptive feed forward control circuit and power supply for a television comprises a circuit for supplying energy from a source to a load, the load having energy requirements which vary in response to an input signal, for example a video signal. A feedback circuit generates a first correction signal indicative of a difference between an operating voltage or current level and a reference level. A neural network generates a second correction signal indicative of anticipated energy requirement variation by processing information in present values of the input signal. A control circuit, for example a pulse width modulating circuit, is responsive to the correction signals for controlling operation of the energy supplying circuit. The first and second correction signals are combined by a summing circuit. The neural network comprises a first signal adaptive circuit for the input signal and a second signal adaptive circuit for a processed version of the input signal.

Abstract: In a vertical sawtooth generator of a D.C. coupled vertical deflection circuit, a vertical deflection amplifier generates a sawtooth signal. Magnitudes of the sawtooth signal in first and second instants of its trace period are determined in accordance with first and second D.C. signals, respectively. The first and second D.C. signals are adjusted during service to control the raster height and the raster centering such that while the raster height is adjusted, raster centering is not significantly affected, and vice versa.

Abstract: A first phase locked loop generates a first timing signal at a first horizontal synchronizing frequency corresponding to a horizontal synchronizing component in a video signal. A converter circuit derives from the first timing signal a second timing signal, having a second frequency at a multiple of the first frequency and subject to a variation in frequency at a rate corresponding to the first frequency. A second phase locked loop comprises a comparator, a low pass filter, a controllable oscillator and a horizontal output deflection stage receives the second timing signal, which can be asymmetric within the period of the first timing signal, and a feedback signal in accordance with the second frequency. The controllable oscillator generates a horizontal synchronizing signal at the second frequency.

Abstract: A sawtooth signal generator of a D.C. coupled vertical deflection circuit is responsive, during service mode of operation, to a first signal at a D.C. level that is indicative of vertical centering. During the service mode operation, the generation of the sawtooth signal is disabled and, instead, the generator generates a D.C. signal that is D.C. coupled via a vertical deflection amplifier to a vertical deflection winding in a manner to position an electron beam at the vertical center of a display screen.

Abstract: The length of the retrace portion of a vertical sawtooth signal is controlled by a microprocessor. In this way, the same type of an integrated circuit that includes the sawtooth generator can be used for generating the sawtooth signal required either for a switch or a non-switch vertical deflection circuit output stage.

Abstract: Convergence correction waveforms are generated for multiple vertical formats. One of a number of vertical formats is selected for displaying a video signal. The vertical formats differ by respective vertical scanning rates, respective vertical scanning heights, or both. A set of convergence correction values corresponding to a plurality of raster locations is stored for each of the different vertical scanning heights. An interpolation control value is stored for each of the vertical scanning frequencies. An interpolator is responsive to different ones of the control values for generating a different set of intermediate convergence correction values for each of the vertical scanning frequencies, from each of the sets of stored convergence correction values. The interpolator generates the intermediate convergence correction values between horizontally and vertically spaced ones of the raster locations.

Abstract: A television apparatus comprises a video display having a wide format display ratio, for example approximately 16:9. A deflection circuit generates first and second selectable rasters having a common horizontal scan width corresponding to the display but having first and second vertical heights respectively, for example nominal and overscanned vertical heights. A control circuit selects one of the first and second rasters for displaying pictures from wide format display ratio video sources and conventional format display ratio video sources respectively, for example 16:9 and 4:3. A picture from the wide format display ratio video source is substantially uncropped and a picture from the conventional format display ratio video source is expanded and cropped. One of the vertical formats provides substantially no image aspect ratio distortion of the pictures as displayed. The other one of the vertical formats provides substantially no cropping of the pictures as displayed.

Abstract: A parabola generator for geometric correction of a television raster, comprises: a resettable circuit for generating a repetitive ramp signal and a resettable integrator for generating a repetitive parabola signal from said repetitive ramp signal. A first resetting circuit initializes the ramp circuit at a frequency related to a scanning frequency. An auxiliary resetting circuit initializes the integrator prior to integrating each repetitive ramp. The auxiliary resetting circuit minimizes timing errors from variations of the ramp signal due to transient conditions. In one embodiment, the scanning period is a horizontal scanning period and the ramp and parabola circuits are reset at the end of each horizontal scanning interval. In this case, the first and auxiliary resetting circuits are responsive to horizontal retrace pulses, for example the leading edges of the horizontal retrace pulses. A further circuit modulates the periodically reset parabolic signal at a vertical scanning rate.

Abstract: An input signal at a horizontal frequency is coupled to a deflection circuit through an isolation transformer during a power-on operation but not during a power-off operation. A voltage at a horizontal deflection frequency is developed in a linearity inductor of the deflection circuit. The voltage in the linearity inductor is rectified to produce a rectified signal that is coupled to an input terminal of a regulator oscillator of a power supply. The rectified signal is coupled to the regulator oscillator in an electrically nonisolated manner with respect to electrical shock hazard isolation and is electrically isolated by the transformer from the input signal. The regulator oscillator generates trigger pulses for controlling the switching operation of an SCR switch of the power supply to produce an output supply voltage that energizes the deflection circuit.

Abstract: A horizontal deflection circuit output stage generates a retrace pulse in a tertiary winding of a flyback transformer. A flyback pulse that is substantially wider than the retrace pulse is produced in a winding of a second transformer that is coupled in series with the tertiary winding such that the retrace pulse occurs when a peak portion of the flyback pulse is already relatively "flat". The amplitude of the flyback pulse is controlled in a negative feedback loop for stabilizing an ultor voltage.

Abstract: A convergence control system for a television apparatus, for example a projection television, comprises: a plurality of channels, each channel having a digital memory for storing a set of grid coordinate values defining a convergence correction grid; and, a pair of multiplying digital to analog converters for the grid coordinate values. A single circuit for generating sequential digital addresses is coupled to each of the channels for outputting the grid coordinate values from each of the digital memories to respective multiplying digital to analog converters of the channel. The values of respective horizontal grid lines are supplied to only one of the multiplying digital to analog coverters. A single waveform generator develops a pair of analog waveforms of complementary phase for modulating respective multiplying digital to analog converters of each pair in each channel. The sum of the modulating waveforms is constant.

Abstract: A circuit provides North-South pincushion correction and gullwing compensation in a raster display of a television apparatus. A correction circuit generates a generally parabolic, horizontal rate correction signal to correct for North-South pincushion distortion. A gullwing compensation circuit is coupled to the correction circuit and forms a feedback path therein for amplitude modifying the correction signal to further correct for gullwing distortion. The gullwing compensation circuit amplitude modifies the generally parabolic signal as a function of itself, achieving an equilibrium condition. A vertical deflection circuit drives a vertical deflection coil with the gullwing compensated correction signal. The correction circuit comprises a ramp waveform generator having a controllable current source generating a constant component of current for pincushion correction and a variable component of current responsive to the feedback signal for gullwing compensation.

Abstract: A dual power source output amplifier comprises at least one pair of first and second input voltage sources of like polarity, operating at low and high voltage magnitude levels respectively relative to one another, and selectively operably coupled to an output stage for driving a load, for example a convergence yoke coil, in low and high voltage modes respectively. The first voltage input source is coupled to the output stage in the low voltage mode. A circuit for directly sensing the output voltage couples a biasing voltage level to the output signal for generating a high voltage demand control signal which varies directly with the output voltage. A switchable voltage regulator couples regulated high voltage from the second voltage input source to the output stage in the high voltage mode, responsive to the high voltage demand control signal. The output stage operates substantially linearly in both voltage modes.

Abstract: A high voltage regulator circuit for maintaining the ultor voltage applied to a picture tube of a television receiver apparatus provides an auxiliary voltage signal for compensation of variations in the ultor voltage caused by variations in the beam current. An improved phase control circuit controls the phase position of the pulses of the auxiliary voltage signal so that they lag with only the leading parts thereof overlapping the retrace voltage signal pulses, in order to prevent the introduction of fluctuations in the ultor voltage due to secondary ringing.