Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Abstract: Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Abstract: An integrated circuit structure includes a substrate, an interconnect stack, a first memory array, and a source line. The interconnect stack is over the substrate. The first memory array is over the interconnect stack and includes memory elements stacked in a vertical direction each comprising a conductive layer. The first memory array further includes a memory layer electrically connecting to the conductive layers of the memory elements and extending downwardly from a topmost one of the conductive layers to a lowermost one of the conductive layers; and a channel layer extending along a sidewall of the memory layer. The source line is in contact with a top end of the channel layer and laterally extends across the first memory array.

Abstract: A memory device includes a substrate, a first conductive stripe disposed on the substrate and extending along a first direction, a second conductive stripe disposed on the first conductive stripe, a first pillar element and a spacer. The second conductive stripe extends along a second direction intersected with the first direction. A thickness of the second conductive stripe is greater than a thickness of the first conductive stripe, and the second conductive stripe is an integral structure. The first pillar element is disposed at an intersection between the first conductive stripe and the second conductive stripe, and extends from a top surface of the first conductive stripe to a bottom surface of the second conductive stripe along a third direction intersected with the first direction and the second direction. The first pillar element includes a switching layer and a memory layer corresponding to a first level.

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a memory element, a spacer structure, and an upper element structure. The memory element includes a lower memory layer and an upper memory layer on the lower memory layer. The spacer structure is on a sidewall surface of the lower memory layer. The upper element structure is electrically connected on the upper memory layer. A recess is defined by a lower surface of the upper element structure, an upper surface of the lower memory layer and a sidewall surface of the upper memory layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer includes a first conductive film. The semiconductor structure includes a first landing pad disposed on the first conductive film. The first landing pad has a first pad sidewall facing toward the second stair layer, and a second pad sidewall opposite to the first pad sidewall. The second pad sidewall includes an inclined sidewall portion.

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer comprises a first conductive film. The semiconductor structure includes a landing pad disposed on the first conductive film. The landing pad has a first pad sidewall facing toward the second stair layer, a first lateral gap distance between an upper portion of the first pad sidewall and the second stair layer is smaller than a second lateral gap distance between a lower portion of the first pad sidewall and the second stair layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a bottom dielectric layer continuously disposed on the substrate. The semiconductor structure further includes a plurality of stacks disposed on the bottom dielectric layer. Each of the stacks includes gate electrodes and semiconductor layers disposed alternately. The semiconductor structure further includes a plurality of source/drain structures disposed on the bottom dielectric layer and between the stacks. The semiconductor structure further includes a plurality of conductors landed on highest gate electrodes of the stacks.

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure comprises a channel element. The channel element comprises a substrate portion and a vertical channel portion. The vertical channel portion is adjoined on the substrate portion. The substrate portion and the vertical channel portion both comprise single crystal silicon.

Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Abstract: A memory device and a manufacturing for the same are provided. The memory device comprises a channel line, word lines, a first switch, and a second switch. Memory cells for a memory string are defined at intersections between the channel line and the word lines. The first switch is electrically connected with the channel line. The second switch is electrically connected with the channel line. The first switch is electrically connected between the second switch and the memory cells.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

Abstract: Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

Abstract: An inductor structure and a manufacturing method for the same are provided. The inductor structure includes conductive layers and conductive elements. The conductive layers overlap in a vertical direction. Each of the conductive elements is coupled between two conductive layers of the conductive layers.

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure comprises a channel element. The channel element comprises a substrate portion and a vertical channel portion. The vertical channel portion is adjoined on the substrate portion. The substrate portion and the vertical channel portion both comprise single crystal silicon.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer comprises a first conductive film. The semiconductor structure includes a landing pad disposed on the first conductive film. The landing pad has a first pad sidewall facing toward the second stair layer, a first lateral gap distance between an upper portion of the first pad sidewall and the second stair layer is smaller than a second lateral gap distance between a lower portion of the first pad sidewall and the second stair layer.

Abstract: A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stack disposed on the substrate, wherein the stack includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the upper surface of the substrate along a first direction; a channel layer penetrating the stack along the first direction, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction; and a memory layer disposed between the channel layer and the second conductive layer.