Patents by Inventor Erh-Kun Lai

Erh-Kun Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950786
    Abstract: A 3D memory includes a plurality of first access line levels, a plurality of second access line levels and a plurality of memory cell levels, the memory cell levels being disposed between corresponding first access line levels and second access line levels. The first access line levels include a plurality of first access lines extending in a first direction, and a plurality of remnants of a first sacrificial material disposed between the first access lines. The second access line levels include a plurality of second access lines extending in a second direction and a plurality of remnants of a second sacrificial material disposed between the second access lines. The memory cell levels include an array of memory pillars disposed in the cross-points between the first access lines and the second access lines in adjacent first and second access line levels.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 16, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Chiao-Wen Yeh
  • Patent number: 10937832
    Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 2, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10916560
    Abstract: A memory device comprises a stack of conductive strips separated by insulating layers on a substrate, and a vertical channel structure disposed in a hole through the stack of conductive strips to the substrate. A vertical channel structure is disposed in a hole through the stack of conductive strips to the substrate. Charge storage structures are disposed at cross points of the conductive strips and the vertical channel structure, the charge storage structures including multiple layers of materials. The insulating layers have sidewalls recessed from the vertical channel structure. A charge storage layer of the multiple layers of materials of the charge storage structures lines sidewalls of the insulating layers. Dielectric material is disposed between the vertical channel structure and the charge storage layer on sidewalls of the insulating layers.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: February 9, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10910393
    Abstract: A memory device comprises a plurality of stacks of word lines alternating with insulating strips, the stacks being separated by trenches, the word lines extending in a first direction. A plurality of columns of vertical conductive structures is disposed in the trenches between adjacent stacks. Multi-layer films of memory material and channel material are disposed on sidewalls of word lines on at least one side of the trenches between adjacent vertical conductive structures in the plurality of vertical conductive structure, the channel material in ohmic contact with the vertical conductive structures. At locations of vertical conductive structures in the plurality of vertical conductive structures, the sidewalls of the word lines are recessed between insulating strips in the stacks to form recesses on the sidewalls of the word lines to isolate the word lines from vertical conductive structures.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 2, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Publication number: 20200343252
    Abstract: A memory device comprises a plurality of stacks of word lines alternating with insulating strips, the stacks being separated by trenches, the word lines extending in a first direction. A plurality of columns of vertical conductive structures is disposed in the trenches between adjacent stacks. Multi-layer films of memory material and channel material are disposed on sidewalls of word lines on at least one side of the trenches between adjacent vertical conductive structures in the plurality of vertical conductive structure, the channel material in ohmic contact with the vertical conductive structures. At locations of vertical conductive structures in the plurality of vertical conductive structures, the sidewalls of the word lines are recessed between insulating strips in the stacks to form recesses on the sidewalls of the word lines to isolate the word lines from vertical conductive structures.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10818729
    Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 27, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Ming-Hsiu Lee, Chiao-Wen Yeh
  • Patent number: 10811602
    Abstract: Memory devices based on tungsten oxide memory elements are described, along with methods for manufacturing such devices. A memory device includes a plug extending upwardly from a top surface of a substrate through a dielectric layer; a bottom electrode having tungsten on an outside surface, the bottom electrode extending upwardly from a top surface of the plug; an insulating material in contact with the tungsten on the outside surface of, and surrounding, the bottom electrode; a memory element on an upper surface of the bottom electrode, the memory element comprising a tungsten oxide compound and programmable to at least two resistance states; and a top electrode overlying and contacting the memory element. The plug has a first lateral dimension, and the bottom electrode has a lateral dimension parallel with the first lateral dimension of the plug that is less than the first lateral dimension.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: October 20, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Dai-Ying Lee, Feng-Min Lee
  • Publication number: 20200328223
    Abstract: A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 15, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Publication number: 20200328224
    Abstract: A memory device comprises a plurality of stacks of bit lines alternating with insulating strips over an insulating layer on a substrate, and a plurality of vertical gate structures disposed between the stacks. Vertical channel structures and memory elements are disposed between outside surfaces of the vertical gate structures and sidewalls of insulating strips in the stacks of bit lines. The vertical channel structures provide channels between adjacent bit lines in the stacks. A plurality of word line transistors is disposed over and connected to respective vertical gate structures. A plurality of word lines is disposed over and connected to the word line transistors. The memory device comprises circuitry connected to the bit lines to apply bit line and source line voltages to the bit lines.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10763306
    Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: September 1, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Dai-Ying Lee, Erh-Kun Lai
  • Patent number: 10720426
    Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 21, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Kuang-Hao Chiang, Dai-Ying Lee
  • Publication number: 20200227432
    Abstract: A memory device comprises a stack of conductive strips separated by insulating layers on a substrate, and a vertical channel structure disposed in a hole through the stack of conductive strips to the substrate. A vertical channel structure is disposed in a hole through the stack of conductive strips to the substrate. Charge storage structures are disposed at cross points of the conductive strips and the vertical channel structure, the charge storage structures including multiple layers of materials. The insulating layers have sidewalls recessed from the vertical channel structure. A charge storage layer of the multiple layers of materials of the charge storage structures lines sidewalls of the insulating layers. Dielectric material is disposed between the vertical channel structure and the charge storage layer on sidewalls of the insulating layers.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 16, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10636812
    Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips. The plurality of stacks of conductive strips includes a plurality of intermediate levels of conductive strips configured as word lines and an upper level of conductive strips configured as string select lines. A plurality of first patterned conductors is disposed above the plurality of stacks of conductive strips. A plurality of linking elements connects conductive strips in respective intermediate levels in the plurality of intermediate levels of conductive strips to first patterned conductors in the plurality of first patterned conductors. The linking elements in the plurality of linking elements include switches responsive to signals in conductive strips in the upper level of conductive strips.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: April 28, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10593875
    Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point. The memory cells in the stacks include confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 17, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Publication number: 20190393268
    Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun LAI, Hsiang-Lan LUNG
  • Patent number: 10515810
    Abstract: A method for manufacturing a memory device comprises forming an initial silicide layer, including depositing and annealing a precursor metal over a layer of silicon material on a top surface of a stack of conductive strips in amounts effective to result in a majority of the initial silicide layer being a mono-silicon silicide of the precursor metal. The method comprises depositing and annealing additional silicon material over the initial silicide layer in amounts effective to result in formation of di-silicon silicide of the precursor metal to form a landing pad on the top surface of the stack of conductive strips, the formation of the di-silicon silicide of the precursor metal consuming mono-silicon silicide of the initial silicide layer so a majority of a silicide of the landing pad is di-silicon silicide.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: December 24, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Publication number: 20190386213
    Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point. The memory cells in the stacks include confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun LAI, Hsiang-Lan LUNG
  • Patent number: 10497714
    Abstract: A 3D memory device includes a substrate, a multi-layers stack, at least one memory structure and an etching stop structure. The substrate has a trench. The multi-layers stack includes a first extending portion forming a non-straight angle with a bottom surface of the trench and a second extending portion, wherein both of the first extending portion and the second extending portion include a plurality of conductive layers and a plurality of insulating layers alternatively stacked in the trench. The memory structure is formed in the first extending portion. The etching stop structure is at least partially disposed in the second extending portion and has a material identical to that of the memory structure.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 3, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Publication number: 20190355903
    Abstract: A 3D memory includes a plurality of first access line levels, a plurality of second access line levels and a plurality of memory cell levels, the memory cell levels being disposed between corresponding first access line levels and second access line levels. The first access line levels include a plurality of first access lines extending in a first direction, and a plurality of remnants of a first sacrificial material disposed between the first access lines. The second access line levels include a plurality of second access lines extending in a second direction and a plurality of remnants of a second sacrificial material disposed between the second access lines. The memory cell levels include an array of memory pillars disposed in the cross-points between the first access lines and the second access lines in adjacent first and second access line levels.
    Type: Application
    Filed: January 28, 2019
    Publication date: November 21, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsiang-Lan LUNG, Erh-Kun LAI, Chiao-Wen YEH
  • Publication number: 20190355790
    Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.
    Type: Application
    Filed: December 27, 2018
    Publication date: November 21, 2019
    Inventors: Hsiang-Lan LUNG, Erh-Kun LAI, Ming-Hsiu LEE, Chiao-Wen YEH