Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a conductive layer, a conductive architecture and a dielectric layer. The conductive layer defines adjacent first openings. The conductive architecture surrounds a portion of the conductive layer between the first openings. The dielectric layer separates the conductive layer and the conductive architecture.

Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming an insulation layer on an access device followed by forming vias through the insulation layer to expose the first and second access device terminals. First and second interlayer conductors extending through the vias are formed next. Top surfaces of the interlayer conductors are oxidized to form oxide layers. The oxide layer on the first interlayer conductor forms a memory layer. On top of the insulation layer a layer of protection metal is formed covering the oxide layers. The layer of protection metal is patterned and etched to form a top electrode layer covering the memory layer. The oxide layer on the second interlayer conductor is removed. Parallel first and second access lines are then formed on the top electrode layer and the second interlayer conductor, respectively.

Abstract: A semiconductor structure and a manufacturing method of the same are disclosed. The semiconductor structure includes a conductive layer, a conductive strip, a dielectric layer, and a conductive element. The conductive layer has a first conductive material. The conductive strip is in the same level as the conductive layer and has a second conductive material. The second conductive material is adjoined with the first conductive material having a conductivity characteristic different from a conductivity characteristic of the second conductive material. The conductive element crisscrosses the conductive strip and separated from the conductive strip by the dielectric layer.

Abstract: A memory device includes a first metal layer and a second metal layer, a metal oxide layer disposed between the first metal layer and the second metal layer, and at least one oxygen control layer disposed between the metal oxide layer and at least one of the first metal layer and the second metal layer. The at least one oxygen control layer has a graded oxygen content.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises the following steps. First, a stack of alternate sacrificial layers and insulating layers is formed on a bottom layer on a substrate. Then, a plurality of first holes and a plurality of second holes are formed through the stack concurrently. In the semiconductor structure as formed by the embodied method, the first holes and the second holes are equally spaced apart from each other at least in an arranged direction.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a conductive layer, a conductive architecture and a dielectric layer. The conductive layer defines adjacent first openings. The conductive architecture surrounds a portion of the conductive layer between the first openings. The dielectric layer separates the conductive layer and the conductive architecture.

Abstract: A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided, comprising. A multi-layer on a substrate is formed, and the multi-layer comprises plural first dielectric layers and second dielectric layers arranged alternately. The multi-layer is then patterned to form plural first patterned stacks and spaces between the first patterned stacks, wherein one of the first patterned stacks has a width of F0 while the one of the spaces has a width of Fs. In one embodiment, F0 is equal to or more than 2 times Fs. Parts of the second dielectric layers of one of the first patterned stacks are removed, so as to form plural first cavities in the first patterned stack. Then, the first cavities in the first patterned stack are filled with conductors.

Abstract: A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided, comprising. A multi-layer on a substrate is formed, and the multi-layer comprises plural first dielectric layers and second dielectric layers arranged alternately. The multi-layer is then patterned to form plural first patterned stacks and spaces between the first patterned stacks, wherein one of the first patterned stacks has a width of FO while the one of the spaces has a width of Fs. In one embodiment, FO is equal to or more than 2 times Fs. Parts of the second dielectric layers of one of the first patterned stacks are removed, so as to form plural first cavities in the first patterned stack. Then, the first cavities in the first patterned stack are filled with conductors.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The method includes following steps. A first gate structure is formed on a substrate in a first region. A protecting layer is formed covering the first gate structure. A second gate structure is formed on the substrate in second region exposed by the protecting layer and adjacent to the first region.

Abstract: A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. A plurality of vertical active strips is formed between the plurality of stacks. Charge storage structures are formed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. Gate dielectric, having a different composition than the charge storage structures, is formed in interface regions at cross-points between the vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips.

Abstract: A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.

Abstract: A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.

Abstract: For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.

Abstract: A memory includes a doped substrate well, a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well. A series arrangement including a plurality of memory cells is coupled on a first end by a first switch to a bit line and coupled on a second end by a second switch to a source line contact pad. The source line contact pad is connected to the substrate connector and to at least one of the interlayer connectors in the set of interlayer connectors. A supply line is connected to the set of interlayer connectors. A plurality of word lines is coupled to the plurality of memory cells. Circuitry is coupled to the supply line and to the doped substrate well and configured to bias the supply line and the doped substrate well with different bias conditions.

Abstract: The present invention further provides a string select line (SSL) of a three-dimensional memory array, including: a dielectric substrate; an SSL structure disposed on the dielectric substrate, wherein the SSL structure includes a plurality of dielectric layers and a plurality of first conductive layers, the dielectric layers and the first conductive layers stacked alternatively; a second conductive layer covering sidewalls and a top portion of the SSL structure; and an oxide layer disposed between the first conductive layers and the second conductive layer, and contacting with the first conductive layers and the second conductive layer.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

Abstract: A 3D memory structure and a manufacturing method of the same are provided. The 3D memory structure includes a substrate, a plurality of stacked structures, a plurality of charge trapping layers, a plurality of bit lines, and a plurality of stair structures. The stacked structures are formed on the substrate, and each of the stacked structures includes a plurality of gates and a plurality of gate insulators alternately stacked on the substrate. The charge trapping layers are formed on the sidewalls of the stacked structures. The bit lines are arranged orthogonally over the stacked structures, the surfaces of the bit lines crossing the stacked structures for forming a plurality of memory elements. The stair structures, each electrically connected to the different gates, are stacked on the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.