Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate having a trench, a stacked structure, an etching stop structure, a plurality of memory structure, and a first filled slit groove formed in the stacked structure. The stacked structure has a horizontal extended region and a vertical extended region extending along a sidewall of the trench. The stacked structure includes a plurality of conductive layer s and a plurality of insulating layers interlacedly stacked in the trench. The etching stop structure is formed in the vertical extended region. The memory structures vertically penetrate through the conductive layers and the insulating layers in the horizontal extended region. The conductive layers and the insulating layers in the vertical extended region are formed on the etching stop structure and located between the etching stop structure and the first filled slit groove.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises an access device, a dielectric layer, a barrier layer, a first interlayer conductor, a first barrier liner, a second interlayer conductor, a second barrier liner, a memory element and a top electrode layer. The access device has two terminals. The dielectric layer covers the access device. The barrier layer is disposed on the dielectric layer. The first and second interlayer conductors are connected to the two terminals, respectively. The first and second barrier liners are disposed on sidewalls of the first and second interlayer conductors, respectively. The memory element is disposed on the first interlayer conductor. The top electrode layer is disposed on the barrier layer and the memory element and covers the memory element.

Abstract: A semiconductor structure and a manufacturing method of the same are disclosed. The semiconductor structure includes a conductive layer, a conductive strip, a dielectric layer, and a conductive element. The conductive layer has a first conductive material. The conductive strip is in the same level as the conductive layer and has a second conductive material. The second conductive material is adjoined with the first conductive material having a conductivity characteristic different from a conductivity characteristic of the second conductive material. The conductive element crisscrosses the conductive strip and separated from the conductive strip by the dielectric layer.

Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. A bottom insulating layer is formed on a substrate. Two stacked structures are formed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched. Part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of connecting portions. The stacks are disposed on the substrate. Each of the stacks comprises alternately-stacked conductive layers and insulating layers. The memory layers are disposed on sidewalls of the stacks, respectively. The channel layers are disposed on the memory layers, respectively, wherein each of the channel layers comprises a surface being exposed. The connecting portions connect the surface of each of the channel layers to the substrate, respectively.

Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. A bottom insulating layer is formed on a substrate. Two stacked structures are formed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched. Part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.

Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, stacks, a blocking layer-trapping layer-tunneling layer structure, channel layers, a first insulating material and a dielectric layer. The stacks are formed on the substrate. Each stack comprises a group of alternating conductive strips and insulating strips as well as a first string select line formed on the group. The blocking layer-trapping layer-tunneling layer structure and the channel layers are formed conformally with the stacks. The first insulating material is formed between the stacks and covers portions of the channel layers. The dielectric layer is formed on portions of the channel layers that are not covered by the first insulating material. The semiconductor structure further comprises second string select lines formed between the stacks on the first insulating material, wherein the second string select lines are separated from the channel layers by the dielectric layer.

Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of multi-layered pillars formed on a substrate and spaced apart from each other, a plurality of first conductors formed between the adjacent multi-layered pillars, a plurality of charging-trapping layers formed on the substrate and on the sidewalls of the multi-layered pillars for separating the first conductor and the multi-layered pillars, and a second conductor formed on the first conductors and on the charging-trapping layers. One of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately. The top surfaces of the first conductors are higher than the top surfaces of the multi-layered pillars so as to create a plurality of receiving trenches respectively on the multi-layered pillars. The second conductor fills up the receiving trenches on the multi-layered pillars.

Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer.

Abstract: A memory device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom level of conductive strips, a plurality of intermediate levels of conductive strips, and a top level of conductive strips. A reference conductor is disposed in a level between the bottom level of conductive strips and a substrate, isolated from the substrate by a layer of insulating material, and isolated from the bottom level by another layer of insulating material. A plurality of vertical active strips is disposed between the plurality of stacks in electrical contact with the substrate, and with the reference conductor. Charge storage structures are disposed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate levels and the vertical active strips. A bias circuit is configured to provide different bias arrangements to the reference conductor and the substrate.

Abstract: A method for fabricating a memory device is provided: A multi-layer stack is formed on a substrate. The multi-layer stack is then patterned to form plural trenches extending along a first direction to define plural ridge-shaped stacks each of which comprises at least one conductive strip. Next, a memory layer and a channel layer are formed in sequence on bottoms and sidewalls of the trenches. A sacrifice layer is formed to fulfill the trenches. Subsequently, portions of the sacrifice layer, the memory layer and the channel layer formed in the trenches are removed to form plural openings exposing a portion of the substrate therefrom. After removing the remaining sacrifice layer, portions of the memory layer and the channel layer formed on the ridge-shaped stacks are patterned to form an interconnection between two adjacent trenches through two of the openings formed in the two adjacent trenches.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate having a trench, a stacked strip structure formed in the trench, and at least a conductive structure. The stacked strip structure includes a plurality of interlaced conductive strips and insulating strips. Each of the conductive strips has a horizontal conductive segment and two vertical conductive segments connected to the corresponding horizontal conductive segment. Each of the insulating strips has a horizontal insulating segment and two vertical insulating segments. The conductive structure is electrically connected to at least one of the conductive strips. The stacked strip structure has a horizontal stacked portion corresponding to the horizontal conductive segments and two vertical stacked portions corresponding to the vertical conductive segments, wherein a width of the vertical stacked portions is larger than a thickness of the horizontal stacked portion.

Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of multi-layered pillars formed on a substrate and spaced apart from each other, a plurality of first conductors formed between the adjacent multi-layered pillars, a plurality of charging-trapping layers formed on the substrate and on the sidewalls of the multi-layered pillars for separating the first conductor and the multi-layered pillars, and a second conductor formed on the first conductors and on the charging-trapping layers. One of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately. The top surfaces of the first conductors are higher than the top surfaces of the multi-layered pillars so as to create a plurality of receiving trenches respectively on the multi-layered pillars. The second conductor fills up the receiving trenches on the multi-layered pillars.

Abstract: A memory device includes a first metal layer and a second metal layer, a metal oxide layer disposed between the first metal layer and the second metal layer, and at least one oxygen control layer disposed between the metal oxide layer and at least one of the first metal layer and the second metal layer. The at least one oxygen control layer has a graded oxygen content.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a stack of alternate conductive layers and insulating layers, an opening, an oxide layer and a conductor. The stack is formed on the substrate. The opening penetrates through the stack. The oxide layer is formed on a sidewall of the opening. The conductor is filled into the opening. The conductor is separated from the sidewall of the opening by only the oxide layer.

Abstract: A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a N+ type semiconductor material or a P+ type semiconductor material, and the memory and the top electrode produce a self-rectified property.