Abstract: A system for limiting deflection of an exhaust sidewall liner on a variable geometry exhaust duct uses a spacer and a T-bolt. The system connects the exhaust sidewall liner to the static structure on a variable geometry exhaust duct. The spacer includes a chimney having a first side and a second side opposite of the first side, an aperture extending from the first side to the second side, a flange disposed on the first side, and at least one anti-rotation tab disposed on the second side near an edge of the second side. The T-bolt includes an elongated shaft that extends along an axis and having a diameter, and a head having at least one straight edge connected to an end of the shaft. The at least one straight edge engages with the anti-ration tab, thereby preventing rotation of the stud T-bolt about the axis.

Abstract: An augmentor vane assembly of a gas turbine engine with an additively manufactured augmentor vane, the additively manufactured augmentor vane having a vane wall with integral longitudinal wall passages formed therein, at least one of the integral longitudinal wall passages including at least one entrance aperture and at least one exit aperture, the at least one exit aperture transverse to the integral longitudinal wall passage.

Abstract: A system for limiting deflection of an exhaust sidewall liner on a variable geometry exhaust duct uses a spacer and a T-bolt. The system connects the exhaust sidewall liner to the static structure on a variable geometry exhaust duct. The spacer includes a chimney having a first side and a second side opposite of the first side, an aperture extending from the first side to the second side, a flange disposed on the first side, and at least one anti-rotation tab disposed on the second side near an edge of the second side. The T-bolt includes an elongated shaft that extends along an axis and having a diameter, and a head having at least one straight edge connected to an end of the shaft. The at least one straight edge engages with the anti-ration tab, thereby preventing rotation of the stud T-bolt about the axis.

Abstract: A gaspath component includes a flowpath body. A cooling plenum is disposed within the flowpath body. The cooling plenum includes a first region configured to receive a cooling flow and a second region configured to expel the cooling flow from the flowpath body. A metering obstruction is positioned between the first region and the second region and is configured to meter a flow of coolant through the cooling plenum.

Abstract: An augmentor vane assembly includes an additively manufactured augmentor vane and a fuel line additively manufactured within the augmentor vane. A method of manufacture including additively manufacturing an augmentor vane having a wall that forms an internal volume therein; and additively manufacturing a fuel line within the augmentor vane that extends through the internal volume.

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Abstract: An aerospace component includes an augmentor vane and a fuel line additively manufactured within the augmentor vane. A method of manufacture including additively manufacturing an augmentor vane wall that forms an internal volume therein; and additively manufacturing a fuel line within the augmentor vane and extends through the internal volume.

Abstract: An aerospace component includes a wall with an integral longitudinal wall passage formed therein, the integral longitudinal wall passage including at least one entrance apertures and at least one exit aperture, the exit aperture transverse to the integral longitudinal wall passage. The aerospace component may be additively manufactured.

Abstract: A gaspath component includes a flowpath body. A cooling plenum is disposed within the flowpath body. The cooling plenum includes a first region configured to receive a cooling flow and a second region configured to expel the cooling flow from the flowpath body. A metering obstruction is positioned between the first region and the second region and is configured to meter a flow of coolant through the cooling plenum.

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Abstract: An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and a second dielectric layer on the first dielectric layer and the bottom plate, and a thin film top plate disposed on the second dielectric layer. The thin film top plate and bottom plate are composed of thin film resistive layers, such as sichrome, which also are utilized to form back end thin film resistors having various properties. Interconnect conductors of a metallization layer contact the top and bottom plates through corresponding vias.

Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

Abstract: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor.

Abstract: An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a semiconductor substrate (1), a first thin film resistor (3) disposed on the first oxide layer (2), and a second oxide layer (14) disposed over the first oxide layer (2) and first thin film resistor (3). A second thin film resistor (15) is formed on the second oxide layer (14) and a third oxide layer (16) is formed over the second thin film resistor (15) and the second oxide layer (14). Interconnect metallization elements (12A,B & 22A,B) disposed on at least one of the second (14) and third (16) oxide layers electrically contact the circuit element (4), terminals of the first thin film resistor (3), and terminals of the second thin film resistor (15), respectively, through corresponding contact openings through at least one of the second (14) and third (16) oxide layers.

Abstract: A thin film resistor structure includes a plurality of thin film resistor sections. Conductive vias (5) are disposed on a first end of each of the thin film resistor sections, respectively. The first conductor (2) is connected to the vias of the first end, and a second conductor (3) is connected to vias on a second end of each of the thin film resistor sections. A distribution of a parameter of a batch of circuits including the thin film resistor structure indicates a systematic error in resistance values. Based on analysis of the distribution and the circuit, or more of the vias are individually moved at the layout grid level by a layout grid address unit to reduce the systematic error by making corresponding adjustments on a via reticle of a mask set used for making the circuits. Expensive laser trimming of thin film resistors of the circuit is thereby avoided.

Abstract: An integrated circuit thin film resistor structure includes a first dielectric layer (18A) disposed on a semiconductor layer (16), a first dummy fill layer (9A) disposed on the first dielectric layer (18B), a second dielectric layer (18C) disposed on the first dummy fill layer (9A), the second dielectric layer (18B) having a first planar surface (18-3), a first thin film resistor (2) disposed on the first planar surface (18-3) over the first dummy fill layer (9A). A first metal interconnect layer (22A,B) includes a first portion (22A) contacting a first head portion of the thin film resistor (2). A third dielectric layer (21) is disposed on the thin film resistor (2) and the first metal interconnect layer (22A,B). Preferably, the first thin film resistor (2) is symmetrically aligned with the first dummy fill layer (9A). In the described embodiments, the first dummy fill layer is composed of metal (integrated circuit metallization).

Abstract: A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over the first dummy fill layer. A thin film resistor (2) is formed on the second dielectric layer (18D). A first inter-level dielectric layer (21A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (22A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (2).

Abstract: A method of improving nucleation during depositing of a film (2) on a surface (18-3) of a wafer, including performing a planarizing operation on the surface (18-3), the planarizing operation resulting in generation of dangling chemical bonding sites on the surface, depositing a dielectric layer (18D) on the planarized surface (18-3) to cover the dangling chemical bonding sites to thereby produce a more uniform surface for nucleation of subsequently deposited resistive film material, and depositing a film (2) of resistive material on the dielectric layer (18D), whereby more uniform nucleation results in the film (2) being very uniform. The film of resistive material is deposited on the dielectric layer directly after the depositing of the dielectric layer, without any further treatment of the dielectric layer (18D).