Patents by Inventor Eric Beyne

Eric Beyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098299
    Abstract: A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.
    Type: Application
    Filed: September 30, 2020
    Publication date: April 1, 2021
    Inventors: Frank Holsteyns, Eric Beyne, Christophe Lorant, Simon Braun
  • Patent number: 10886252
    Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 5, 2021
    Assignee: IMEC vzw
    Inventors: Lan Peng, Soon-Wook Kim, Eric Beyne, Gerald Peter Beyer, Erik Sleeckx, Robert Miller
  • Publication number: 20200402950
    Abstract: A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 24, 2020
    Inventors: Lin Hou, Jaber Derakhshandeh, Eric Beyne, Ingrid De Wolf, Giovanni Capuz
  • Patent number: 10797016
    Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 6, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Vikas Dubey, Eric Beyne, Giovanni Capuz
  • Publication number: 20200203309
    Abstract: A method of using sacrificial structures in a mold substrate for packaging a first die and one or more second dies or stacks thereof is disclosed. The method allows testing of the first die prior to mounting the second dies, without requiring a TSV insert. In one aspect, a block of sacrificial material is embedded together with the first die in a first mold substrate and to one side of the first die. The removal of the block creates an opening. The method is configured so that contacts are exposed at the bottom of the opening, the contacts being electrically connected to corresponding contacts on the first die. This may be realized by bonding both the die and the sacrificial block to a redistribution layer, or by mounting a bridge device between the first die and the block prior to a first overmolding applied for producing the first mold substrate.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 25, 2020
    Inventor: Eric Beyne
  • Publication number: 20200185566
    Abstract: An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (?LED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 11, 2020
    Inventors: Soeren Steudel, Alexander Mityashin, Eric Beyne, Maarten Rosmeulen
  • Publication number: 20200152508
    Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 14, 2020
    Inventors: Anne Jourdain, Nouredine Rassoul, Eric Beyne
  • Patent number: 10636739
    Abstract: An integrated circuit (IC) chip having power and ground rails incorporated in the front end of line (FEOL) is disclosed. In one aspect, these power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip. The connection from the buried interconnects to the source and drain areas is established by local interconnects. These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced. In a further aspect, a power delivery network (PDN) of the IC is located in its entirety on the backside of the chip. The PDN is connected to the buried interconnects through suitable connections, for example metal-filled through-semiconductor vias or through silicon vias.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 28, 2020
    Assignee: IMEC vzw
    Inventors: Eric Beyne, Julien Ryckaert
  • Publication number: 20200118840
    Abstract: A method for packaging semiconductor dies by overmolding is disclosed. The dies are embedded in a substrate of a mold material, and cavities are produced in the mold substrate by producing 3D structures of a sacrificial material prior to the overmolding step. Afterwards, the sacrificial material is removed to thereby create cavities in the mold substrate. A conformal layer is produced on the 3D structures prior to overmolding, and the mold substrate is thinned to expose an upper surface of the 3D structures. The conformal layer is not removed when the sacrificial structures are removed. In this way, the conformal layer remains on the surfaces of the mold substrate inside the cavity. In one aspect, the conformal layer may have a protective function, useful in the production of packages including dies which come into contact with fluid substances.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 16, 2020
    Inventor: Eric Beyne
  • Patent number: 10334755
    Abstract: A liquid cooling system for cooling an electronic device comprising a chip or a chip package comprising a chip is described. The liquid cooling system comprises an inlet plenum comprising a coolant feeding channel oriented substantially parallel with the plane of a main surface to be cooled of the chip and a plurality of inlet cooling channels fluidically connected to the coolant feeding channel and arranged vertically for impinging a liquid coolant directly on said main surface of the chip. The vertically oriented inlet cooling channels are substantially parallel to vertically oriented outlet cooling channels and are separated by a thermally isolating material. The liquid cooling system further comprises at least one cavity wherein a plurality of inlet and outlet cooling channels end. The cavity is arranged for allowing interaction between the liquid coolant and the main surface of the chip and thus comprises a heat transfer region.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 25, 2019
    Assignee: IMEC VZW
    Inventors: Herman Oprins, Vladimir Cherman, Eric Beyne
  • Patent number: 10332850
    Abstract: Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 25, 2019
    Assignee: IMEC
    Inventors: Eric Beyne, Wenqi Zhang, Geraldine Jamieson, Bart Swinnen
  • Patent number: 10271796
    Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 30, 2019
    Assignee: IMEC
    Inventors: Maria Op De Beeck, Eric Beyne, Philippe Soussan
  • Patent number: 10256183
    Abstract: The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP comprises portions of a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: April 9, 2019
    Assignee: IMEC
    Inventors: Mikael Detalle, Eric Beyne
  • Patent number: 10170450
    Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Eric Beyne, Joeri De Vos, Stefaan Van Huylenbroeck
  • Patent number: 10141284
    Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 27, 2018
    Assignee: IMEC vzw
    Inventors: Soon-Wook Kim, Lan Peng, Patrick Verdonck, Robert Miller, Gerald Peter Beyer, Eric Beyne
  • Patent number: 10066303
    Abstract: The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: September 4, 2018
    Assignees: IMEC VZW, GLOBALFOUNDRIES INC.
    Inventors: Eric Beyne, Joeri De Vos, Jaber Derakhshandeh, Luke England, George Vakanas
  • Publication number: 20180247914
    Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient.
    Type: Application
    Filed: February 28, 2018
    Publication date: August 30, 2018
    Inventors: Lan Peng, Soon-Wook Kim, Eric Beyne, Gerald Peter Beyer, Erik Sleeckx, Robert Miller
  • Publication number: 20180145030
    Abstract: An integrated circuit (IC) chip having power and ground rails incorporated in the front end of line (FEOL) is disclosed. In one aspect, these power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip. The connection from the buried interconnects to the source and drain areas is established by local interconnects. These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced. In a further aspect, a power delivery network (PDN) of the IC is located in its entirety on the backside of the chip. The PDN is connected to the buried interconnects through suitable connections, for example metal-filled through-semiconductor vias or through silicon vias.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 24, 2018
    Inventors: Eric Beyne, Julien Ryckaert
  • Patent number: 9978710
    Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 22, 2018
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Vikas Dubey, Eric Beyne, Jaber Derakhshandeh
  • Publication number: 20180130765
    Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 10, 2018
    Inventors: Vikas Dubey, Eric Beyne, Giovanni Capuz