Abstract: An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices at its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

Abstract: In one aspect, a receiving substrate is produced, configured to receive thereon one or more dies by hybrid bonding in one or more first landing areas and one or more dies by solder bonding in one or more second landing areas. In the two types of landing areas, contact pads are formed which are embedded in a dielectric layer or a stack of dielectric layers, enabling hybrid bonding in the hybrid bonding landing areas. The contact pads in the solder landing areas are configured to receive solder material directly on the contact pads after bonding of the hybrid bonded dies, without requiring the formation of under bump metal pads. In another aspect, at least the solder contact pads include two layers, a bottom layer and a top layer, the bottom layer being formed of a material exhibiting slower intermetallic compound formation when reacting with solder than the material of the top layer.

Abstract: In one aspect, a receiving substrate is produced, configured to receive thereon one or more dies by hybrid bonding in one or more first landing areas and/or one or more dies by solder bonding in one or more second landing areas. In the two types of landing areas, contact pads are formed which are embedded in a dielectric layer or a stack of dielectric layers, enabling hybrid bonding in the hybrid bonding landing areas. The contact pads in the solder landing areas are configured to receive solder material directly on the contact pads after bonding of the hybrid bonded dies, without requiring the formation of under bump metal pads. In another aspect, at least the solder contact pads include two layers, a bottom layer and a top layer, the bottom layer being formed of a material exhibiting slower intermetallic compound formation when reacting with solder than the material of the top layer.

Abstract: An example embodiment includes a semiconductor component. The semiconductor component includes a semiconductor substrate and at least one layer of dielectric material. The layer has a planar upper surface. An electrical conductor is arranged in a first trench and formed in the layer of dielectric material. The first trench includes a base and a pair of upstanding sidewalls. The conductor includes a stack of alternate ferromagnetic and non-magnetic layers. The stack extends along the base and the sidewalls of the first trench so that the stack defines a second trench inside the first trench. The conductor also includes an electrically conductive portion that integrally fills the second trench.

Abstract: A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.

Abstract: A cooling device configured to be mounted in close proximity to an electronic component that is to be cooled is provided. In one aspect, the device includes impingement channels and return channels for guiding a flow of cooling fluid towards and away from a cooled surface of the electronic component. The device also includes a heat exchanger and a pump, so that the flow cycle of a cooling fluid is fully confined within the device itself. The impingement channels, the return channels, and the heat exchanger are integrated in a common housing, which includes an inlet opening and an outlet opening for coupling the device to a refrigerant loop. The pump may be a micropump mounted directly on the housing and coupled to the inlet and outlet openings in the housing. A cooling system including the device and the refrigerant loop is also provided.

Abstract: A semiconductor product is provided. The semiconductor product comprises a first wafer (21) comprising a first active pad array (21a), and at least a second wafer (22) comprising at least a second active pad array (22a). In this context, the first wafer (21) and the at least one second wafer (22) are bonded together. In addition to this, the first wafer (21) and/or the at least one second wafer (22) comprises a transition area (23) being directly adjacent to the first active pad array (21a) and/or the at least one second active pad array (22a).

Abstract: A semiconductor including a plurality of structured contacts suitable for forming electrical connections to respective contacts of another semiconductor component, wherein each of said structured contacts comprises a planar contact surface and a plurality of upright tube-shaped structures extending outward from the planar contact surface is disclosed. The tube-shaped structures may be arranged in a regular array on the respective contact surfaces and are produced by a sequence of steps including the patterning of a dielectric layer formed on the front surface of the component, said patterning resulting in openings in said dielectric layer, and the deposition of a conformal layer on said patterned dielectric layer, thereby lining the bottom and sidewalls of the openings. The conformal layer may be removed from the upper surface of the dielectric layer and the material of said layer is removed selectively with respect to the conformal layer, resulting in said tube-shaped structures.

Abstract: A layer of semiconductor devices is produced on the frontside of a crystalline semiconductor substrate, in regions separated by dielectric-filled cavities formed previously. Additional layers are then formed on the device layer. The substrate is then flipped and bonded face down to a second substrate, following by the thinning of the crystalline first substrate from the backside. The thinning proceeds as far as possible without removing the full thickness of the first substrate anywhere across its surface. After this, an anisotropic etch is performed to remove additional material of the first substrate. The in-plane dimensions of the device regions separated by the dielectric-filled cavities are specified so that the anisotropic etch is stopped by a crystallographic plane of the substrate material or by the dielectric material in the cavities, before it can reach the devices on the frontside.

Abstract: Superconducting solder bumps are produced on a qubit substrate by electrodeposition. The substrate comprises qubit areas, and superconducting contact pads connected to the qubit areas. First a protection layer is formed on the substrate, and patterned so as to cover at least the qubit areas. Then one or more thin layers are deposited conformally on the patterned protection layer, the thin layers comprising at least a non-superconducting layer suitable for acting as a seed layer for the electrodeposition of the solder bumps. The seed layer is removed locally in areas which lie within the surface area of respective contact pads. This is done by producing and patterning a mask layer, so that openings are formed therein, and by removing the seed layer from the bottom of the openings. The solder bumps are formed by electrodeposition of the solder material on the bottom of the openings. After the formation of the solder bumps, the seed layer and the protection layer are removed.

Abstract: The disclosed technology is related to semiconductor components, including a multilayer structure with a plurality of MIM capacitors. The capacitors are realized as an assembly of capacitors in the form of a stack of at least three electrically conductive layers, separated by dielectric layers and formed conformally on a topography defined by a plurality of dielectric pillars distributed on a conductive bottom plate formed on a first level of the multilayer interconnect structure. By realizing a height difference between different pillars or different groups of pillars, the intermediate ayers of the stack become available for contacting the layers by via connections.

Abstract: A micro-electronic component, for example an integrated circuit chip, is provided. In one aspect, the component includes a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion at its front side. A back side power delivery network (PDN) is present at the back side of the component, with via connections connecting the PDN to the FEOL and BEOL portions. The back side PDN includes a “dry part” and a “wet part,” where the dry part includes multiple interconnect levels of the PDN embedded in a dielectric material. The “wet part” includes the remaining PDN levels which are not embedded in a dielectric but which are part of a manifold structure configured to receive therein a flow of cooling fluid in order to remove heat generated by the devices in the FEOL portion.

Abstract: A method for bonding and interconnecting micro-electronic components is provided. In one aspect, two substrates are bonded to form a 3D assembly of micro-electronic components. Both substrates include first cavities open to the respective bonding surfaces, and at least one substrate includes a second cavity that is larger than the first cavities in terms of its in-plane dimensions, and possibly also in terms of its depth. An electrically conductive layer is produced on each substrate. The layer is patterned in the second cavity, and a micro-electronic device is fabricated in the second cavity. The bonding surfaces are planarized, removing the conformal layer from the bonding surfaces, and the substrates are bonded to form the assembly, where the first cavities of both substrates are brought into mutual contact to form an electrical connection. Device in the large cavities may be contacted through TSV connections or back end of line interconnect levels.

Abstract: A cooling device configured to be mounted in close proximity to an electronic component that is to be cooled is provided. In one aspect, the device includes impingement channels and return channels for guiding a flow of cooling fluid towards and away from a cooled surface of the electronic component. The device also includes a heat exchanger and a pump, so that the flow cycle of a cooling fluid is fully confined within the device itself. The impingement channels, the return channels, and the heat exchanger are integrated in a common housing, which includes an inlet opening and an outlet opening for coupling the device to a refrigerant loop. The pump may be a micropump mounted directly on the housing and coupled to the inlet and outlet openings in the housing. A cooling system including the device and the refrigerant loop is also provided.

Abstract: A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies.

Abstract: A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures.

Abstract: The present disclosure relates to a quantum bit (qubit) chip. The qubit chip includes two or more qubit wafers arranged along a common axis and one or more spacer elements. The spacer elements and the qubit wafers are alternately arranged on the common axis. The qubit chip further includes a conductive arrangement configured to electrically connect the two or more qubit wafers, where the conductive arrangement includes at least one superconducting via per each qubit wafer of the two or more qubit wafers and each spacer element of the one or more spacer elements, the at least one superconducting via passing through the qubit wafer or spacer element.

Abstract: A semiconductor component, for example an integrated circuit chip, including a semiconductor substrate having active devices at the front side thereof and I/O terminals at the back side of the component, is provided. In one aspect, the terminals are connected to the active devices through TSV connections and buried rails in an area of the substrate that is separate from the area in which the active devices are located. The I/O TSV connections are located in a floating well of the substrate that is separated from the rest of the substrate by a second well formed of material of the opposite conductivity type compared to the material of the floating well. The second well includes at least one contact configured to be coupled to a voltage that is suitable for reverse-biasing the junction between the floating well and the second well.

Abstract: A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.

Abstract: An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices on its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.