Abstract: There is provided a processing apparatus, method and computer program. The apparatus comprising: decode circuitry to decode instructions; and processing circuitry to apply vector processing operations specified by the instructions. The decode circuitry is configured to, in response to a vector combining instruction specifying a plurality of source vector registers each comprising source data elements in a plurality of data element positions, one or more further source vector registers, and one or more destination registers, cause the processing circuitry to, for each data element position: extract first source data elements from the data element position of each source vector register; extract second source data elements from the one or more further source vector registers; generate a result data element by combining each element of the first source data elements and the second source data elements; and store the result data element to the data element position of the one or more destination registers.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: Data processing apparatus comprises vector processing circuitry to access an array register having at least n×n storage locations, where n is an integer greater than one, the vector processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry. The instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, for a vector of n vector elements, a set of n storage locations each having a respective array location in the array register. The array location accessed for a given vector element of the vector is defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

Abstract: There is provided a processing apparatus, method and computer program. The apparatus comprising: decode circuitry to decode instructions; and processing circuitry to apply vector processing operations specified by the instructions. The decode circuitry is configured to, in response to a vector combining instruction specifying a plurality of source vector registers each comprising source data elements in a plurality of data element positions, one or more further source vector registers, and one or more destination registers, cause the processing circuitry to, for each data element position: extract first source data elements from the data element position of each source vector register; extract second source data elements from the one or more further source vector registers; generate a result data element by combining each element of the first source data elements and the second source data elements; and store the result data element to the data element position of the one or more destination registers.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: Apparatuses, methods, programs, and complex number processing instructions are provided to support vector processing operations on input data vectors comprising a plurality of input data items at respective positions in the input data vectors. In response to the instructions at least one first set of data items is extracted from alternating positions in a first source register and at least one second set of data items is extracted from alternating positions in the second source register, wherein consecutive data items in the first and second source registers comprise alternating real and imaginary components of respective sets of complex numbers. A result set of complex number components is generated using the two sets of data items as operands, and the result set of complex number components is one of a real part and an imaginary part of a complex number result of the complex number operation applied to the two sets of complex numbers.

Abstract: An apparatus, method and computer program are described, the apparatus comprising processing circuitry configured to execute software, and an interface configured to receive, from the processing circuitry, a configuration request from first software requesting configuration of a virtualised device. In response to the configuration request, the interface is configured to forward a mediated request to the processing circuitry, and the mediated request comprises a request that second software having a higher privilege level than the first software determines a response to the configuration request received from the first software.

Abstract: A data processing system and method of data processing are provided. The system comprises first and second data processing agents and data storage shared coherently between the both data processing agents to store a message data structure to provide a message channel between them. A further data storage is accessible to both data processing agents to store message channel metadata, which provides message status information for the message channel. The message channel metadata is one of a plurality of message channel metadata types defined for a corresponding plurality of message channel types between the first and second data processing agents, and at least one of the first and second data processing agents is responsive to an initialization trigger to establish the message channel with a selected message channel type.

Abstract: Apparatuses, methods, programs, and complex number processing instructions are provided to support vector processing operations on input data vectors comprising a plurality of input data items at respective positions in the input data vectors. In response to the instructions at least one first set of data items is extracted from alternating positions in a first source register and at least one second set of data items is extracted from alternating positions in the second source register, wherein consecutive data items in the first and second source registers comprise alternating real and imaginary components of respective sets of complex numbers. A result set of complex number components is generated using the two sets of data items as operands, and the result set of complex number components is one of a real part and an imaginary part of a complex number result of the complex number operation applied to the two sets of complex numbers.

Abstract: A data processing system and a method of data processing are provided. The system comprises a first data processing agent, a second data processing agent, and a third data processing agent. Each of the second and third data processing agents have access to one or more caches. A messaging mechanism conveys a message from the first data processing agent to one of the second and third data processing agents specified as a message destination agent in the message. A stashing manager monitors the messaging mechanism and selectively causes data associated with the message to be cached for access by the message destination agent in a cache of the one or more caches in dependence on at least one parameter associated with the message and at least one stashing control parameter defined for a link from the first data processing agent to the message destination agent.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: An apparatus, method and computer program are described, the apparatus comprising processing circuitry configured to execute software, and an interface configured to receive, from the processing circuitry, a configuration request from first software requesting configuration of a virtualised device. In response to the configuration request, the interface is configured to forward a mediated request to the processing circuitry, and the mediated request comprises a request that second software having a higher privilege level than the first software determines a response to the configuration request received from the first software.

Abstract: A data processing system and method of data processing are provided. The system comprises first and second data processing agents and data storage shared coherently between the both data processing agents to store a message data structure to provide a message channel between them. A further data storage is accessible to both data processing agents to store message channel metadata, which provides message status information for the message channel. The message channel metadata is one of a plurality of message channel metadata types defined for a corresponding plurality of message channel types between the first and second data processing agents, and at least one of the first and second data processing agents is responsive to an initialization trigger to establish the message channel with a selected message channel type.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A data processing system and a method of data processing are provided. The system comprises a first data processing agent, a second data processing agent, and a third data processing agent. Each of the second and third data processing agents have access to one or more caches. A messaging mechanism conveys a message from the first data processing agent to one of the second and third data processing agents specified as a message destination agent in the message. A stashing manager monitors the messaging mechanism and selectively causes data associated with the message to be cached for access by the message destination agent in a cache of the one or more caches in dependence on at least one parameter associated with the message and at least one stashing control parameter defined for a link from the first data processing agent to the message destination agent.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.