Patents by Inventor Eric Biscondi

Eric Biscondi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11113091
    Abstract: An apparatus, method and computer program are described, the apparatus comprising processing circuitry configured to execute software, and an interface configured to receive, from the processing circuitry, a configuration request from first software requesting configuration of a virtualised device. In response to the configuration request, the interface is configured to forward a mediated request to the processing circuitry, and the mediated request comprises a request that second software having a higher privilege level than the first software determines a response to the configuration request received from the first software.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 7, 2021
    Assignee: Arm Limited
    Inventors: Alexandre Romana, Mario Torrecillas Rodriguez, Eric Biscondi
  • Patent number: 11106513
    Abstract: A data processing system and method of data processing are provided. The system comprises first and second data processing agents and data storage shared coherently between the both data processing agents to store a message data structure to provide a message channel between them. A further data storage is accessible to both data processing agents to store message channel metadata, which provides message status information for the message channel. The message channel metadata is one of a plurality of message channel metadata types defined for a corresponding plurality of message channel types between the first and second data processing agents, and at least one of the first and second data processing agents is responsive to an initialization trigger to establish the message channel with a selected message channel type.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 31, 2021
    Assignee: Arm Limited
    Inventors: Robert Gwilym Dimond, Eric Biscondi, Mario Torrecillas Rodriguez, Paul Stanley Hughes
  • Publication number: 20210026628
    Abstract: Apparatuses, methods, programs, and complex number processing instructions are provided to support vector processing operations on input data vectors comprising a plurality of input data items at respective positions in the input data vectors. In response to the instructions at least one first set of data items is extracted from alternating positions in a first source register and at least one second set of data items is extracted from alternating positions in the second source register, wherein consecutive data items in the first and second source registers comprise alternating real and imaginary components of respective sets of complex numbers. A result set of complex number components is generated using the two sets of data items as operands, and the result set of complex number components is one of a real part and an imaginary part of a complex number result of the complex number operation applied to the two sets of complex numbers.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 28, 2021
    Inventors: Eric BISCONDI, Mbou EYOLE
  • Patent number: 10877891
    Abstract: A data processing system and a method of data processing are provided. The system comprises a first data processing agent, a second data processing agent, and a third data processing agent. Each of the second and third data processing agents have access to one or more caches. A messaging mechanism conveys a message from the first data processing agent to one of the second and third data processing agents specified as a message destination agent in the message. A stashing manager monitors the messaging mechanism and selectively causes data associated with the message to be cached for access by the message destination agent in a cache of the one or more caches in dependence on at least one parameter associated with the message and at least one stashing control parameter defined for a link from the first data processing agent to the message destination agent.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: December 29, 2020
    Assignee: ARM LIMITED
    Inventors: Robert Gwilym Dimond, Eric Biscondi, Paul Stanley Hughes, Mario Torrecillas Rodriguez
  • Publication number: 20200319881
    Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 8, 2020
    Inventors: Timothy David Anderson, Duc Quang Bui, Mujibur Rahman, Joseph Raymond Michael Zbiciak, Eric Biscondi, Peter Dent, Jelena Milanovic, Ashish Shrivastava
  • Publication number: 20200293350
    Abstract: An apparatus, method and computer program are described, the apparatus comprising processing circuitry configured to execute software, and an interface configured to receive, from the processing circuitry, a configuration request from first software requesting configuration of a virtualised device. In response to the configuration request, the interface is configured to forward a mediated request to the processing circuitry, and the mediated request comprises a request that second software having a higher privilege level than the first software determines a response to the configuration request received from the first software.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventors: Alexandre ROMANA, Mario Torrecillas RODRIGUEZ, Eric BISCONDI
  • Publication number: 20200241943
    Abstract: A data processing system and method of data processing are provided. The system comprises first and second data processing agents and data storage shared coherently between the both data processing agents to store a message data structure to provide a message channel between them. A further data storage is accessible to both data processing agents to store message channel metadata, which provides message status information for the message channel. The message channel metadata is one of a plurality of message channel metadata types defined for a corresponding plurality of message channel types between the first and second data processing agents, and at least one of the first and second data processing agents is responsive to an initialization trigger to establish the message channel with a selected message channel type.
    Type: Application
    Filed: September 4, 2018
    Publication date: July 30, 2020
    Inventors: Robert DIMOND, Eric BISCONDI, Mario RODRIGUEZ, Paul HUGHES
  • Patent number: 10628156
    Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy David Anderson, Duc Quang Bui, Mujibur Rahman, Joseph Raymond Michael Zbiciak, Eric Biscondi, Peter Dent, Jelena Milanovic, Ashish Shrivastava
  • Publication number: 20190114262
    Abstract: A data processing system and a method of data processing are provided. The system comprises a first data processing agent, a second data processing agent, and a third data processing agent. Each of the second and third data processing agents have access to one or more caches. A messaging mechanism conveys a message from the first data processing agent to one of the second and third data processing agents specified as a message destination agent in the message. A stashing manager monitors the messaging mechanism and selectively causes data associated with the message to be cached for access by the message destination agent in a cache of the one or more caches in dependence on at least one parameter associated with the message and at least one stashing control parameter defined for a link from the first data processing agent to the message destination agent.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 18, 2019
    Inventors: Robert Gwilym DIMOND, Eric BISCONDI, Paul Stanley HUGHES, Mario Torrecillas RODRIGUEZ
  • Publication number: 20150154024
    Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
    Type: Application
    Filed: July 9, 2014
    Publication date: June 4, 2015
    Inventors: Timothy David Anderson, Duc Quang Bui, Mujibur Rahman, Joseph Raymond Michael Zbiciak, Eric Biscondi, Peter Dent, Jelena Milanovic, Ashish Shrivastava
  • Patent number: 8880855
    Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy D Anderson, Duc Quang Bui, Eric Biscondi, Shriram D Moharil, Mujibur Rahman, Soujanya Narnur, Peter Richard Dent, Ashish Rai Shrivastava
  • Patent number: 8392789
    Abstract: A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Eric Biscondi, David Hoyle, Tod David Wolf
  • Patent number: 8151031
    Abstract: A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: April 3, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Eric Biscondi, David J. Hoyle, Tod D. Wolf
  • Publication number: 20120079247
    Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 29, 2012
    Inventors: Timothy D. Anderson, Duc Quang Bui, Eric Biscondi, Shriram D. Moharil, Mujibur Rahman, Soujanya Narnur, Peter Richard Dent, Ashish Rai Shrivastava
  • Patent number: 7995640
    Abstract: Apparatus and method for optimizing interpolation in the despreader data-path of a wireless telecommunications network employing Code Division Multiple Access (CDMA) technology. A base station dynamically evaluates its configuration to determine an interpolator location. The location of the interpolator in a despreader data-path is dynamically selected. A received signal is interpolated. The despread received signals are combined, and further processing is applied to the combined signal. To enhance system performance, the interpolator may, be located at least to perform chip-sample interpolation per antenna stream at chip rate, chip-sample interpolation per user at chip rate, or symbol-sample interpolation per user at sub-symbol rate.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: August 9, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Pierre Bertrand, David J. Hoyle, Eric Biscondi
  • Publication number: 20110029756
    Abstract: A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 3, 2011
    Inventors: Eric Biscondi, David Hoyle, Tod David Wolf
  • Publication number: 20100169735
    Abstract: Apparatus for optimizing low-density parity check (“LDPC”) decoding in a processor is disclosed herein. A processor in accordance with the present disclosure includes an LDPC decoder row update execution unit. The LDPC decoder row update execution unit accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel. The execution unit is activated by execution of an LDPC row update instruction. The execution unit adds a minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values to produce a row update value.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eric BISCONDI, David J. HOYLE, Tod D. WOLF
  • Publication number: 20100005372
    Abstract: A digital signal processor for decoding Trellis based channel encoding stages based on radix-4 stages comprising means for rearranging the input and output data in Radix-4 Viterbi decoding to make inter-stage Trellis data movement suitable for use in the digital signal processor.
    Type: Application
    Filed: July 1, 2009
    Publication date: January 7, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Peter R. Dent, Eric Biscondi, David Hoyle
  • Publication number: 20100002793
    Abstract: A high data width accelerator, comprising computer instructions for calculating at least a portion of a trace-back during a trellis computation, wherein the calculation allows faster trace-back
    Type: Application
    Filed: July 1, 2009
    Publication date: January 7, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Peter R. Dent, Eric Biscondi, David Hoyle
  • Publication number: 20090254718
    Abstract: A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.
    Type: Application
    Filed: March 6, 2009
    Publication date: October 8, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eric Biscondi, David J. Hoyle, Tod D. Wolf