Abstract: Digital isolators operable in multiple power modes are described. The digital isolators include a low power mode, in which some circuitry of the isolator operates in a lower power state than in other mode(s) of operation or may be deactivated, and in which data communication across the isolator is not permitted. The isolator may wake from the low power mode in response to a detected event or may periodically wake. Circuitry on one side of the isolator may dictate when and how the isolator wakes from a lower power mode.

Abstract: Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

Abstract: Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

Abstract: A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.

Abstract: A receiver system for an on-off key (“OOK”) isolator system may include a pair of receivers. A first receiver may generate a first current signal representing a received OOK signal, and a second receiver may generate a second current signal from a common mode representation of the received OOK signal. The receiver system may include circuitry to compare the first and second current signals and generate an output signal therefrom.

Abstract: A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.

Abstract: A receiver system for an on-off key (“OOK”) isolator system may include a receiver that generates an intermediate current signal based on an OOK input signal. The intermediate current may be provided at a first current level when the input signal has a first OOK state and a second current level when the input signal has a second OOK state. The system also may include an output driver to generate a voltage representation of the intermediate current signal. Performing signal processing in a current domain permits fast transitions between OOK states.

Abstract: A receiver system for an on-off key (“OOK”) isolator system may include a receiver that generates an intermediate current signal based on an OOK input signal. The intermediate current may be provided at a first current level when the input signal has a first OOK state and a second current level when the input signal has a second OOK state. The system also may include an output driver to generate a voltage representation of the intermediate current signal. Performing signal processing in a current domain permits fast transitions between OOK states.

Abstract: A receiver system for an on-off key (“OOK”) isolator system may include a pair of receivers. A first receiver may generate a first current signal representing a received OOK signal, and a second receiver may generate a second current signal from a common mode representation of the received OOK signal. The receiver system may include circuitry to compare the first and second current signals and generate an output signal therefrom.

Abstract: The invention is directed to a multi-bit digital signal isolation system including a plurality of micro-transformers, each having a primary winding and a secondary winding, a transmitter circuit receiving a multi-bit signal and transmitting an encoded logic signal across the plurality of micro-transformers corresponding to the multi-bit signal, the primary winding of each micro-transformer receiving a signal corresponding to one of at least three possible states, and a receiver circuit receiving the encoded logic signal from the secondary windings of the plurality of transformers, decoding the encoded logic signal and reconstructing the received multi-bit signal based upon the decoded signal.

Abstract: The invention is directed to a multi-bit digital signal isolation system including a plurality of micro-transformers, each having a primary winding and a secondary winding, a transmitter circuit receiving a multi-bit signal and transmitting an encoded logic signal across the plurality of micro-transformers corresponding to the multi-bit signal, the primary winding of each micro-transformer receiving a signal corresponding to one of at least three possible states, and a receiver circuit receiving the encoded logic signal from the secondary windings of the plurality of transformers, decoding the encoded logic signal and reconstructing the received multi-bit signal based upon the decoded signal.

Abstract: An sample rate converter for non-audio AES data channels is presented. Channel status (C) information is transferred in 192-bit blocks. Access to received C channel data blocks is allowed, before the blocks are re-transmitted at the output sample rate. This enables users to modify the data, alleviating the effect of data loss caused by different input and output sample frequencies. For U channel status information, U channel status information is transferred as 2×192 bit blocks like the channel status (C) scheme above, as individual information units (IUs), or as messages consisting of 129 IUs. In the latter 2 schemes, the lengths of output inter-IU filler segments or output intemessage filler segments are varied relative to the lengths of inputs inter-IU filler segments or input inter-IU message segments respectively, to compensate for the difference between the input sample frequency and the output sample frequency.

Abstract: A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.

Abstract: A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.

Abstract: A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.