USB isolator with advanced control features
A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.
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Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 8,432,182. The reissue applications are: (1) U.S. patent application Ser. No. 14/697,524, filed Apr. 27, 2015, titled “USB Isolator With Advanced Control Features; (2) U.S. patent application Ser. No. 14/697,528, filed Apr. 27, 2015, titled “USB Isolator With Advanced Control Features; and (3) U.S. patent application Ser. No. 14/697,532, filed Apr. 27, 2015, titled “USB Isolator With Advanced Control Features, each of which is a reissue application of U.S. Pat. No. 8,432,182.
CROSS-REFERENCE TO RELATED APPLICATIONSThis application is a reissue application of U.S. application Ser. No. 12/504,153, filed Jul. 16, 2009, now U.S. Pat. No. 8,432,182, titled “USB Isolator With Advanced Control Features”, which claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 61/164,672, filed on Mar. 30, 2009, and entitled “USB Isolator With Advanced Control Features,” which is herein incorporated by reference in its entirety.
BACKGROUNDIsolators are devices that exchange data signals between two galvanically isolated circuit systems. The circuit systems each operate in different voltage domains, which may include different source potentials and different grounds. Isolation devices may provide data exchange across an isolation barrier, which maintains the galvanic isolation.
Isolation devices have been used for USB communication. These devices commonly include a USB receiver that receives data from a USB cable according to the USB protocol and transmits the received data across an isolation barrier. Although these USB isolators permit USB communication to traverse an isolation barrier, known devices are limited. For example, no known USB isolator performs controlled enumeration or adequately communicates status between upstream and downstream circuit systems. Accordingly, there is a need in the art for a USB isolator with expanded capabilities.
A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent, power-efficient operation, and manage possible communication errors that can arise between the isolated circuit systems.
As illustrated in
The USB transceivers 110.1, 110.2 support bi-directional data communication across connected differential signal lines (UD+/UD− and DD+/DD−) according to the USB protocol. The USB transceivers 110.1, 110.2 recognize various transmission states from data transmitted across the USB signal lines and output received signals to respective isolator transceivers 130.1, 130.2. The isolator transceivers 130.1, 130.2 support bi-directional communication over the isolator devices 120.1-120.4. For example, the isolator transceivers 130.1, 130.2 may convert signals received from the associated USB transceiver 110.1, 110.2 into a form for transmission over the isolator devices 120.1-120.4. The isolator transceivers 130.1, 130.2 also may convert the signals received from the isolator devices 120.1-120.4 into a form for transmission to an associated USB transceiver 110.1, 110.2. In an embodiment, the system 100 will include two pairs of unidirectional isolator devices 120.1-120.2, 120.3-120.4, one pair to support communication in the downstream direction and another pair to support communication in the upstream direction. In such a case, the isolator transmitter units and isolator receiver units are provided in a paired relationship with a corresponding pair of isolator channels (e.g., the isolator transmitter in transceiver 130.1 generates isolator signals for transmission across isolator devices 120.1-120.2 and for reception by the isolator receiver in transceiver 130.2).
Although not illustrated in
According to an embodiment of the present invention, the isolator system 100 also may include an isolator device 140, transmitter 142 and receiver 144 and termination circuit 150 to support enumeration control. The termination circuit 150 may be attached to a connector port into which a USB cable would be inserted. The termination circuit 150 may include one or more pull up resistors R connected to a voltage source (V), a pair of switches 152.1, 152.2 to selectively connect a pull up resistor to one of the upstream USB signal lines UD+ or UD−. The size of the pull up resistors R may be determined by the governing USB standard (e.g., 1.5 kΩ for USB 2.0). Connection of the pull up resistor R to the signal lines is controlled by a switch controller 154 which, in turn, is controlled by an ‘enumeration enable’ signal received on a downstream side of the isolator system 100 and a selection signal (SEL). The selection signal may identify which of the two signal lines UD+ or UD− will be connected to the pull up resistor R. The enumeration enable signal may control timing—when the respective signal line is connected to the pull up resistor R.
As noted, the enumeration enable signal may be received on a downstream side of the isolator system 100. The enumeration enable signal may be received from a downstream peripheral device (not shown) as an express signal; in this case, the isolator system 100 may include an external pin P1 to receive the enumeration enable signal from the peripheral device. Alternatively, the enumeration enable signal may be derived by the downstream transceiver USB 110.2 from activity detected on the downstream USB signal lines DD+ and DD− (shown in phantom in
As illustrated in
Consider the isolator device 100 in operation. Run time operation may be initiated when a downstream peripheral device is first turned on or connected to the upstream device via the upstream USB bus. It is expected that the downstream peripheral device may undertake its own boot up/self test procedure. These procedures, therefore, may define some latency between the time it is turned on to the time the downstream peripheral device is ready to receive data.
When the downstream device is ready to receive data, it may assert the enumeration enable signal to the isolator system 100. The enumeration enable signal propagates through the isolator transmitter unit 142, the isolator device 140 and the isolator receiver unit 144. The isolator transmitter unit may perform signal conversion to condition the signal for transmission via the isolator device 140. The isolator receiver unit 144 may generate a recovered enumeration enable signal from the signal received from the isolator device 140. The recovered enumeration signal is output to the switch control logic 154. The switch control logic 154 may close one of the transistor switches 152.1, 152.2 when it receives the recovered enumeration signal (say, switch 152.2). Closing the switch connects a pull up resistor R to the selected bus line (for example, UD− when switch 152.2 is closed), which signals the upstream device that a device is connected and enumeration should proceed. Accordingly, upstream enumeration control is provided for a downstream device in the isolator system 100.
The USB transceivers 210.1, 210.2 support bi-directional data communication across connected differential signal lines (UD+/UD− and DD+/DD−) according to the USB protocol. The USB transceivers 210.1, 210.2 recognize various transmission states from data transmitted across the USB signal lines and output logic signals to respective isolator transceivers 230.1, 230.2. The isolator transmitter units 232.1, 232.2 may convert input logic signals into a form appropriate for transmission via the isolator devices 220.1, 220.2. The isolator receiver units 234.1, 234.2 may convert signals received from the isolator devices into logic signals. In the embodiment illustrated in
The embodiment shown in
When micro-transformers are used, pulse signals are convenient signals to be transmitted across an isolation barrier. To accommodate the shared isolator configuration of
When two isolator channels are used, the pulse patterns may be combined in a variety of ways. Table 1 illustrates one possible configuration. In this configuration, at least 4 pulse combinations may be reserved to represent the information content that may be carried via the USB run time signals. Other combinations may be used to identify assertion or de-assertion of the enumeration enable signal and the type of selection used.
In Table 1, ‘X’ denotes a don't care condition. Moreover, the ‘disconnect’ state indicates the pull up resistor is to be disconnected and the USB transmitters are to be placed in a high impedance state (not driving the data lines).
Table 2 illustrates another configuration in which pulse assignments are likely to conserve power as compared to the Table 1 case.
Again, ‘X’ denotes a don't care condition. Generally, the ‘J’ and ‘K’ states are the most frequently used over long periods of operation. To save power, the ‘J’ and ‘K’ states are assigned to {channel 1, channel 2} states with minimal pulse activity. SE0 is used much less frequently and, therefore, it is assigned to a {channel 1, channel 2} state with somewhat more pulse activity. SE1 occurs rarely and therefore is assigned to a maximum power {channel 1, channel 2} state.
Consider the isolator device 200 in operation. Again, it is expected that a downstream peripheral device may undertake its own boot up/self test procedure. These procedures, therefore, may define some latency between the time it is turned on to the time the downstream peripheral device is ready to receive data. When the downstream device is ready to receive data, it may assert the enumeration enable signal and the selection signal to the isolator system 200. The enumeration enable and selection signals propagate through the isolator transceiver encoder 236, isolator transmitter unit 232.2, the isolator device 220 and the isolator receiver unit 234.1. The isolator transmitter unit may perform signal conversion to condition the signal for transmission via the isolator device 220. The isolator receiver unit 234.1 may generate a recovered enumeration enable and selection signals from the signal received from the isolator device 220. The recovered enumeration and selection signals are output to the switch control logic 254. The switch control logic 254 may close one of the transistor switches 252.1, 252.2 when it receives the recovered enumeration signal (say, switch 252.2). Closing the switch connects the pull up resistor R to the selected bus line (UD−), which signals the upstream device that a device is connected and enumeration should proceed. Accordingly, upstream enumeration control is provided for a downstream device in the isolator system 200.
As noted above, it is expected that the isolator system and downstream device will be provided as components of a larger consumer device. They may be provided within a common housing. The USB interface provided between the isolator system and the downstream device may not be perceptible to operators of the consumer device. In such implementations, it may not be necessary to provide an interface between the isolator system and the downstream device that conforms to all of the requirements of the USB interface.
A conventional Type A USB connection includes a conductor that is powered at 5 volts. The 5V conductor is powered by a hub device, which permits downstream devices to power themselves from the USB conductor. By contrast, Type B USB connections are prohibited from providing power to the 5V conductor. As noted above, it is expected that the USB isolator proposed herein will be included within a unitary consumer device; it may not be known whether the USB connection to the downstream device will be of Type A or Type B. If Type B connections are to be used, it may be inconvenient for the consumer device to include the 5V conductor of a Type A connection, particularly if the isolator would not use the 5V conductor—it is to be powered from an intermediate voltage (say, 3.3 V). Accordingly, in an embodiment of the present invention, the isolator is designed to be powered by the 5V potential mandated by the USB specification or from the intermediate potential.
Connection configurations may vary as shown in
Voltage regulator control may be accomplished via the following rules:
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- IfVBUS>VTHHI AND VDD<VTHLO, then the voltage regulator is enabled.
- IfVBUS<VTHHI AND VDD>VTHLO, then the voltage regulator is disabled.
- IfVBUS>VTHHI AND VDD>VTHLO, then prior operation of the voltage regulator is maintained.
- IfVBUS<VTHHI AND VDD<VTHLO, the voltage regulator is disabled.
As noted, the operational control may be accomplished by a set/reset latch. Alternatively, the rules could be coded into a state machine, which generates control outputs to the voltage regulator as described above.
In practice, the threshold voltages VTHHI and VTHLO can be set to intermediate levels surrounding the expected VDD values. For example, consider a system in which VDD is 3.3 V and VBUS of a USB bus is 5V. VTHHI may be set to an intermediate potential between VDD and VBUS, for example, 4.2V. VTHLO may be set to a potential close to but lower than VDD, such as 2.9V.
Alternatively, enumeration can be controlled by providing a voltage monitor on the downstream USB interface (not shown). The downstream USB interface 730B includes its own pull down resistors coupled to the DD+/DD− signal lines. A counterpart pull up resistor may be provided at the downstream device which, when connected to one of the D+/D− signal lines, indicates that enumeration may commence and further indicates a speed of the USB connection. When the pull up resistor is connected, a voltage monitor (not shown) at the isolator's downstream USB receiver 732B may detect a voltage change, identify the signal line to which the downstream peripheral device connected its pull up resistor, and relay the information to the upstream termination circuit 760 to cause a similar connection to be made.
In addition to providing controlled USB enumeration, the two circuit sub-systems 710A and 710B work together in coordinated fashion to properly start up, to recover from error conditions, and to manage transmission of USB data back and forth across the isolation devices. To accomplish these control goals, communication between the systems is provided.
There are several associated challenges. First, each circuit sub-system can have its own power supply voltage, and any order of power supply startup is possible (e.g., the upstream-side power supply may start first or the downstream-side power supply may start first). There may be times when only one circuit sub-system 710A or 710B is powered while the other is not, but for all possible startup sequences, the complete system 700 should be working properly by the time both circuit sub-systems 710A and 710B are fully powered. The system 700 should also work during and recover from periods in which one sub-system is fully powered but in the other, the power supply is cycled off and on.
A second challenge arises because the sub-systems are largely isolated from each other, except for limited communication through the isolation devices 720, which have a primary purpose of communicating USB serial data. Although additional, separate isolation devices could be provided to communicate extra ‘control’ information to achieve the control goals, the extra devices would increase die area and cost. Accordingly, it is desired to provide control circuits and communication methods that achieve the control goals using only existing isolator devices 720.
Finally, it is desirable for the sub-system 710A to consume power below a suspend current threshold of 2.5 mA when the system 700 is fully powered but USB busses are idle. This avoids need for a special low-power ‘suspend’ mode, or circuitry to control transitions between the suspend mode and a normal, non-suspended operating mode.
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- RESET 810: In this state, the controller disables the isolator receiver 744A, isolator transmitter 742A and USB transmitter 734A.
- IDLE 820: In this state, the controller enables the isolator receiver, enables the isolator transmitter, and disables the USB transmitter.
- DRIVE DOWNSTREAM PATH 830: In this state, the controller disables the isolator receiver, enables the isolator transmitter and disables the USB transmitter.
- DRIVE UPSTREAM PATH 840: In this state, the controller enables the isolator receiver, disables the isolator transmitter, and enables the USB transmitter.
The RESET state 810 may be reached whenever the controller detects error conditions such as voltage underflows or when the isolator determines an enumeration pull up resistor in the upstream USB interface should be disconnected. The RESET state 810 can be reached from any other state whenever these conditions occur.
The IDLE state 820 can be reached from the RESET state 810 when error conditions discontinue and the enumeration pull up resistor is connected. The IDLE state 820 can be reached from the DRIVE UPSTREAM PATH state 840 when no error conditions are occurring and an end of packet condition or watchdog timeout condition occurs (as discussed below). The IDLE state 820 also can be reached from the DRIVE DOWNSTREAM PATH state 830 when no error conditions are occurring, and an end of packet condition occurs.
The DRIVE DOWNSTREAM PATH state 830 can be reached from the IDLE state 820 when no error conditions are occurring, the controller detects the arrival of data from the USB receiver 732A, or a refresh timer expires (as discussed below). Once the controller enters the DRIVE DOWNSTREAM PATH state 830, it may remain in the state until an end of packet signal (EOP) is encountered in the transmitted signal or an error condition occurs. When an EOP is encountered in the absence of errors, the controller may return to the IDLE state 820.
The DRIVE UPSTREAM PATH state 840 can be reached from the IDLE state 820 when no error conditions are occurring and the controller detects the arrival of data from the isolator receiver 744A. Once the controller enters the DRIVE UPSTREAM PATH state 840, it may remain in the state until an EOP is encountered, or a watchdog timeout occurs, or an error condition occurs. When an EOP is encountered or watchdog timeout occurs in the absence of errors, the controller may return to the IDLE state 82.
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- RESET 910: In this state, the controller disables the isolator receiver 744B, isolator transmitter 742B and the USB transmitter 734B.
- DOWNSTREAM SYSTEM READY 920: In this state, the controller enables the isolator receiver, disables the isolator transmitter and disables the USB transmitter.
- DRIVE DOWNSTREAM PATH 930: In this state, the controller enables the isolator receiver, disables the isolator transmitter, and enables the USB transmitter.
- IDLE 940: In this state, the controller enables the isolator receiver and isolator transmitter, and disables the USB transmitter.
The RESET state 910 may be reached whenever the controller detects error conditions such as voltage underflows or when the isolator determines an enumeration pull up resistor in the upstream USB interface should be disconnected. The RESET state 910 can be reached from any other state whenever these conditions occur.
The DOWNSTREAM SYSTEM READY state 920 can be reached from the RESET state 910 when error conditions discontinue and the enumeration pull up resistor is connected. In this state, the downstream controller 750B may determine that the downstream circuit system 710B is operational. The downstream controller 750B has not yet determined that the upstream circuit system 710A is operational.
The DRIVE DOWNSTREAM PATH state 930 can be reached from either the IDLE state 940 or the DOWNSTREAM SYSTEM READY state 920. In both cases, the controller 750B enters the DRIVE DOWNSTREAM PATH state 930 when the controller 750B detects the arrival of data from the isolator receiver 744B, and no error conditions are occurring. Once the controller 750B enters the DRIVE DOWNSTREAM PATH state 930, it may remain in the state until an EOP is encountered or a watchdog timeout occurs, or an error condition occurs. When an EOP is encountered or the watchdog times out in the absence of errors, the controller 750B may transition to the IDLE state 940.
The IDLE state 940 can be reached from the DRIVE DOWNSTREAM PATH state 930 when no error conditions are occurring, and an end of packet condition or watchdog timeout condition occurs. The IDLE state 940 also can be reached from the DRIVE UPSTREAM PATH state 950 when no error conditions are occurring and an end of packet condition occurs.
The DRIVE UPSTREAM PATH state 950 can be reached from the IDLE state 940 when no error conditions are occurring, the controller 750B detects the arrival of data from the USB receiver 732B, or a refresh timer expires. Once the controller 750B enters the DRIVE UPSTREAM PATH state 950, it may remain in the state until an EOP is encountered or until an error condition occurs. When an EOP is encountered in the absence of errors, the controller 750B may return to the IDLE state 940.
In an embodiment, the refresh circuit 1040 may include a refresh timer 1050, a refresh pulse generator 1060, a multiplexer 1070 and an OR gate. The refresh timer 1050 may count down from the time an edge is detected by the edge detector 1010 or from the time of a prior refresh pulse. The OR gate 1080 may reset the refresh timer 1050 when an edge is detected by the edge detector or when a new refresh pulse is output by multiplexer 1030. The refresh pulse generator 1060 may generate pulses when the refresh timer 1050 expires. The refresh pulse generator 1060 may generate both types of pulses (shown as p1, p2) when the refresh timer expires. The multiplexer 1070 may select one of the two pulses output by the refresh pulse generator 1060 based on a level of the input signal. The multiplexer's output may be input to multiplexer 1030.
In an embodiment, the refresh circuit 1140 may include a refresh timer 1150, a refresh pulse generator 1160, a multiplexer 1170 and an OR gate 1180. The OR gate 1180 may be coupled to the input signal via an edge detector 1190. The refresh timer 1150 may count down from the time an edge is detected in the input signal or from the time of a prior refresh pulse. The OR gate 1180 may reset the refresh timer 1150. The refresh pulse generator 1160 may generate pulses when the refresh timer 1150 expires. The refresh pulse generator 1160 may generate both types of pulses (shown as p1, p2) when the refresh timer expires. The multiplexer 1170 may select one of the two pulses output by the refresh pulse generator 1160 based on a level of the input signal. The multiplexer's output may be input to multiplexer 1130.
An isolator receiver is designed to recognize these pulse patterns and generate corresponding logic transitions. The isolator receiver includes a watchdog timer which is reset if new pulse patterns are received before a ‘watchdog’ interval tW elapses. If the watchdog interval elapses without new pulses being received, the watchdog timer expires and a timeout signal is output. The timeout signal can be communicated to a controller such as the ones shown in
The isolator receiver's watchdog interval is longer than the isolator transmitter's refresh interval. Accordingly, in the absence of transmission errors, pulses are input to the receiver at a sufficiently high frequency to prevent the watchdog timer from timing out. Some exceptions exist, however.
In a USB full/low-speed application, it is helpful to send refresh pulses when the logic state of D+ and D− is something besides the ‘J’ state of the USB 2.0 protocol, and not to send refresh pulses when the state of D+ and D− is ‘J’. If the ‘J’ condition persists for a long time, the watchdog timer will time out, and the receiver's controller will transition to an IDLE state. This is generally desirable as, by convention, USB transmitters are not supposed to actively drive a J onto D+ and D− for arbitrarily long times. Instead, the longest valid ‘actively driven’ J should be 7 USB bit times. So any J input to the isolator system lasting longer than 7 bit times is probably an undriven ‘idle J’ that results when no USB transmitters are driving the USB cable, but pull up and pull down resistors are connected and establish the ‘J’ voltage levels. In the isolator system, the undriven ‘idle’ J should be copied across the isolation barrier. A simple way to do this without using extra isolator devices is with selective use of the isolator ‘refresh’ for only non-J inputs, along with a watchdog timer in the isolator receiver, with timeout interval longer than 7 bit times.
This scheme is also useful for error recovery. If valid USB packets are always transmitted without error through the isolator, the isolator receiver's controller should reach the IDLE state following end-of-packet sequences in the USB data stream. However, if the end-of-packet is not detected due to signal transmission error, the USB transmitter might be left on for longer than desirable after the end-of-packet sequence has occurred. With the selective refresh+watchdog timer feature, if the isolator receiver receives a long-lasting J, the USB transmitter is turned off and the controller reaches the IDLE state at a time corresponding to a watchdog interval after the J began, even if no end-of-packet was detected. This prevents the transmitter from remaining stuck indefinitely in an enabled state, when it should actually be disabled.
Another advantage of this scheme is that it saves power. When the USB D+ and D− are in an idle J state in this scheme, no pulses are transmitted in the isolator devices, minimizing power consumption. If the J's were refreshed, power would be consumed in transmitting pulses though the isolator devices.
During operation the pulse generator 1360 may generate several types of pulses (shown as P1, P2) to the routing logic 1370. The memory 1360 may store patterns of configuration data to be output to the routing logic based on the delayed input data. As shown in
Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.
Claims
1. An isolation system, comprising:
- a plurality of isolation devices bridging an isolation barrier between an upstream side and a downstream side of the isolation barrier,
- a USB interface provided on an upstream side of the isolation barrier, including a termination circuit having a pull up resistor,
- an isolator transceiver coupling the USB interface to the isolation devices, and
- an isolator transmitter provided on a downstream side of the isolation barrier to receive an enumeration control signal, wherein the enumeration control signal propagates through at least one of the isolation devices to the upstream side and controls switching of the pull up resistor in the termination circuit.
2. The isolation system of claim 1, wherein isolation devices are provided for each of a D+ and D− data signal of a USB protocol and a separate isolation device is provided for the enumeration control signal.
3. The isolation system of claim 1, wherein isolation devices are provided for each of a D+ and D− data signal of a USB protocol, and signals are encoded so the enumeration control signal can propagate through said isolation devices along with the D+ and D− data.
4. The isolation system of claim 1, wherein isolation devices are provided for each of a D+ and D− data signal of a USB protocol and are shared with the enumeration control signal.
5. The isolation system of claim 1, wherein the isolation devices are unidirectional isolation devices.
6. The isolation system of claim 1, wherein the isolation devices are bidirectional isolation devices.
7. The isolation system of claim 1, further comprising an input for a selection signal that identifies which one of the D+ and D− data lines is to be connected to the pull up resistor.
8. The isolation system of claim 7, wherein the input is provided on the upstream side of the isolation barrier.
9. The isolation system of claim 7, wherein the input is provided on the downstream side of the isolation barrier.
10. An isolation system, comprising:
- an isolation device bridging an isolation barrier between an upstream side and a downstream side;
- the downstream side including: a downstream USB interface to determine an operating speed of a peripheral device, and an isolator transmitter to transmit a control signal conveying the operating speed across the isolation barrier through the isolation device; and
- the upstream side including: an upstream USB interface with a termination circuit including a pull up resistor, an isolator receiver to receive the control signal from the downstream side and provide the received control signal to a controller, and the controller to control switching of the pull up resistor based on the control signal received by the isolator receiver.
11. The isolation system of claim 10, wherein the isolation device is a first isolation device, and wherein the isolation system further comprises a second isolation device bridging the isolation barrier between the upstream side and the downstream side, wherein the second isolation device is provided for transmitting USB data signals.
12. The isolation system of claim 10, wherein the isolation device is shared for transmission of the control signal and USB data signals.
13. The isolation system of claim 10, further comprising an encoder provided at the downstream side to encode the control signal with USB data signals, wherein the encoded signal is to be transmitted through the isolation device.
14. The isolation system of claim 10, wherein the isolation device is unidirectional.
15. The isolation system of claim 10, wherein the isolation device is bidirectional.
16. The isolation system of claim 10, further comprising a pulse generator to generate the control signal, wherein the control signal is a pulse signal.
17. The isolation system of claim 10, further comprising a refresh timer to maintain one side of the isolation system in a reception state for communication across the isolation barrier during a watchdog interval.
18. A method, comprising:
- determining, at a first side of a galvanically isolated circuit system, an operating speed of a peripheral device connected by a first USB connection to the circuit system,
- transmitting, from the first side of the circuit system to a second side of the circuit system and across an isolation barrier of the circuit system, a control signal identifying the operating speed of the first USB connection, and
- receiving the control signal at the second side of the circuit system using an isolator receiver and providing the received control signal to a controller on the second side of the circuit system;
- controlling, using the controller at the second side of the circuit system, one or more pull up resistors of a second USB interface at the second side according to the control signal received by the isolator receiver.
19. The method of claim 18, further comprising:
- transmitting, from the first side to the second side of the circuit system, USB data signals.
20. The method of claim 19, wherein the USB data signals and the control signal are transmitted through separate isolation devices.
21. The method of claim 19, wherein the USB data signals and the control signal are transmitted through a common isolation device.
22. The method of claim 21, further comprising:
- encoding the control signal with the USB data signals.
23. The method of claim 18, wherein determining the operating speed of the peripheral device includes monitoring signals of the first USB connection.
24. The method of claim 18, wherein the control signal is a pulse signal.
25. The method of claim 18, further comprising:
- maintaining one side of the isolated circuit system in a reception state for communication across the isolation barrier during a watchdog interval.
26. An integrated circuit that is configured to determine an operating speed of an isolated USB, comprising:
- an isolation barrier separating a first side and a second side of the integrated circuit;
- a USB interface to determine an operating speed of a peripheral device;
- an isolator transmitter, on the first side, to transmit a control signal conveying the operating speed across the isolation barrier;
- an isolator receiver, on the second side, to receive the control signal from the first side and provide the control signal to a controller, and
- the controller to control switching a termination circuit based on the control signal received by the isolator receiver.
27. The integrated circuit of claim 26, further comprising an isolation device for transmitting the control signal that is separate from another isolation device for transmitting USB data signals.
28. The integrated circuit of claim 26, wherein an isolation device is shared for the transmission of the control signal and USB data signals.
29. The integrated circuit of claim 26, further comprising an encoder provided at the first side to encode the control signal with USB data signals, wherein the encoded signal is to be transmitted through an isolation device.
30. The integrated circuit of claim 26, further comprising a capacitive isolation device bridging the isolation barrier between the first and second sides.
31. The integrated circuit of claim 26, further comprising a pulse generator to generate the control signal, wherein the control signal is a pulse signal.
32. The integrated circuit of claim 26, further comprising a refresh timer to maintain one side of the integrated circuit in a reception state for communication across the isolation barrier during a watchdog interval.
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Type: Grant
Filed: Apr 27, 2015
Date of Patent: Oct 23, 2018
Assignee: Analog Devices, Inc. (Norwood, MA)
Inventors: Eric C. Gaalaas (Bedford, MA), Mark Stewart Cantrell (Windham, NH)
Primary Examiner: My-Trang Ton
Application Number: 14/697,528
International Classification: H03K 19/003 (20060101);