Abstract: Apparatuses and methods for optimizing rate-distortion costs in a signal are disclosed. An apparatus may comprise a quantization block that may be configured to generate a plurality of candidates for each of a plurality of coefficients. The quantization block may further generate a respective plurality of arcs based, at least in part, on the plurality of candidates. The quantization block may be configured to determine which of the plurality of arcs has a lowest cost using a trellis optimization technique. Fractional bit estimations may be used to calculate rate, and inverse lambda may be used to calculate candidate coefficients.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate an output signal and one or more motion vectors in response to (i) a bitstream signal and (ii) a predictor signal. The second circuit may be configured to generate one or more reference data pixels in response to an address signal and the output signal. The third circuit may be configured to generate the predictor signal and address signal in response to (i) the motion vectors and (ii) the reference data pixels.

Abstract: An apparatus including a control circuit and an encoder circuit. The control circuit may configured to generate a first control signal and a second control signal. The encoder circuit may be configured to (i) receive a plurality of coefficients, the first control signal and the second control signal and (ii) generate an encoded signal in response to the plurality of coefficients, the first control signal and the second control signal. The encoder circuit may be further configured to simultaneously encode run before syntax elements with the plurality of coefficients.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.

Abstract: An apparatus including a test circuit, an output circuit and a control circuit. The test circuit may be configured to generate test data in response to one or more test vectors. The output circuit may be configured to present data in a first mode and prevent presentation of data in a second mode. The output circuit may be configured to switch between the first mode and the second mode in response to a control signal. The control circuit may be configured to generate the control signal according to predetermined criteria for protecting secure data within the apparatus while allowing the test data to be presented.

Abstract: An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) copy a plurality of first reference samples of a first reference image from an external memory, the first reference samples being proximate a first position within the first reference image and (ii) generate a first motion vector corresponding to a first current block of a current image by searching among the first reference samples. The second circuit may be configured to (i) copy a plurality of second reference samples of the first reference image from the external memory, the second reference samples being (a) proximate a second position within the first reference image and (b) non-adjacent the first reference samples and (ii) generate a second motion vector corresponding to the first current block by searching among the second reference samples.

Abstract: An apparatus generally having a reference memory and a motion estimation circuit is disclosed. The reference memory may store reference samples used in a motion estimation of a current block beyond a boundary of a picture. The motion estimation circuit may (i) buffer the reference samples as copied from the reference memory, the reference samples as buffered residing both (a) inside the boundary and (b) inside a search window of the motion estimation, (ii) shift a sub-set of the reference samples to align with a corner of a sub-window, the sub-window being (a) completely within the search window and (b) at least partially outside of the boundary, (iii) fill an empty portion of the sub-window with copies of the reference samples within the sub-set and (iv) generate difference values by comparing the current block against the reference samples within the sub-window a plurality of times.

Abstract: An apparatus including a parsing circuit and a control circuit. The parsing circuit may be configured to generate a plurality of decoded syntax elements in response to (i) a serial bitstream and (ii) a control signal. The control circuit may be configured to generate the control signal in response to the plurality of decoded syntax elements. The parsing circuit may generate the plurality of decoded syntax elements by grouping syntax elements for atomic decoding such that each (i) one or more consecutive syntax elements without context information relevant to the decoding and (ii) a non-zero syntax element presented at the end of each group.

Abstract: A plurality of memory circuits and a logic circuit. The plurality of memory circuits may be configured to store a plurality of pixels. The pixels may be used in a motion estimation stage of a video encoder. The logic circuit may be configured to (i) control which of the pixels are stored in which of the plurality of memory banks and (ii) control accessing of the plurality of pixels.

Abstract: An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of sum values by adding a plurality of pixel difference values between a current block and a reference block, one of the sum values corresponding to each of a plurality of smallest partitions of the current block. The second circuit configured to (i) generate a plurality of intermediate values from the sum values, one of the intermediate values corresponding to each of a plurality of possible partitions of the current block, (ii) store a plurality of lowest values among the intermediate values as the current block is moved through a search window and (iii) generate a motion signal conveying at least one motion vector based on the lowest values.

Abstract: A method for decoding a bitstream is disclosed. The method generally comprises the steps of (A) generating a first signal and a second signal by parsing a common slice in the bitstream, (B) generating a third signal by entropy decoding the first signal, and (C) generating a video signal by combining the second signal and the third signal.

Abstract: A method for transcoding between video streams using different entropy coding, comprising the steps of (A) decoding a first video stream using a first set of entropy codes, and (B) generating a second video stream by entropy encoding the decoded first video stream using a second set of entropy codes. The first set of entropy codes and the second set of entropy codes are configured to represent all valid coefficient values of the first video stream.

Abstract: A method for transcoding between videostreams using different entropy coding, comprising the steps of (A) decoding a first videostream using a first set of entropy codes, and (B) generating a second videostream by entropy encoding the decoded first videostream using a second set of entropy codes. The first set of entropy codes and the second set of entropy codes are configured to represent all valid coefficient values of the first videostream.

Abstract: An apparatus comprising a first circuit, a second circuit, and a watermark detection circuit. The first circuit may be configured to generate a bitstream, wherein the bitstream comprises a watermark message which represents hidden information. The second circuit may be configured to (i) simulate film grain in response to one or more predetermined values on the watermark message and (ii) generate a video output. The watermark detection circuit may be configured to extract hidden information from the decoded video output.

Abstract: A system for reducing storage requirements for content-adaptive binary arithmetic coding (CABAC) is provided. The system includes a transcode engine performing CABAC on a video data stream. The transcode engine receives save data, stops CABAC, and converts the video data stream into sub-network abstraction layer (NAL) unit state data. An entropy state data storage system receiving the sub-NAL unit state data and stores the sub-NAL unit state data. The transcode engine subsequently receives restore data, extracts the sub-NAL unit state data from the entropy state data storage system, and re-starts CABAC on the video stream data.

Abstract: An apparatus including a control circuit and an encoder circuit. The control circuit may configured to generate a first control signal and a second control signal. The encoder circuit may be configured to (i) receive a plurality of coefficients, the first control signal and the second control signal and (ii) generate an encoded signal in response to the plurality of coefficients, the first control signal and the second control signal. The encoder circuit may be further configured to simultaneously encode run before syntax elements with the plurality of coefficients.

Abstract: An apparatus including a test circuit, an output circuit and a control circuit. The test circuit may be configured to generate test data in response to one or more test vectors. The output circuit may be configured to present data in a first mode and prevent presentation of data in a second mode. The output circuit may be configured to switch between the first mode and the second mode in response to a control signal. The control circuit may be configured to generate the control signal according to predetermined criteria for protecting secure data within the apparatus while allowing the test data to be presented.

Abstract: An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) copy a plurality of first reference samples of a first reference image from an external memory, the first reference samples being proximate a first position within the first reference image and (ii) generate a first motion vector corresponding to a first current block of a current image by searching among the first reference samples. The second circuit may be configured to (i) copy a plurality of second reference samples of the first reference image from the external memory, the second reference samples being (a) proximate a second position within the first reference image and (b) non-adjacent the first reference samples and (ii) generate a second motion vector corresponding to the first current block by searching among the second reference samples.