Abstract: A method for controlling an arithmetic codec context is disclosed. The method may include the steps of (A) reading a current value indicating one of a first condition and a second condition corresponding to a current context of a plurality of predetermined contexts, (B) generating an input state matching (i) an initial state in response to the first condition and (ii) an output state in response to the second condition, wherein the initial state has a predetermined value and the output state has a value generated by the method before receiving the current context and (C) generating a current output state by performing an arithmetic code operation on an input signal using the input state.

Abstract: An apparatus for motion estimation generally including a memory and a circuit. The circuit may be configured to (i) search for a first motion vector for a first current block among a plurality of first reference samples, (ii) copy a plurality of second reference samples from the memory and (iii) search for a second motion vector for a second current block among the second reference samples copied from the memory and at least a portion of the first reference samples.

Abstract: An apparatus generally having a first memory and a circuit is disclosed. The first memory may be used for a motion estimation of a current block. The circuit may be configured to (i) determine if a search window for the current block is at least partially outside a boundary of a picture stored in a second memory, (ii) copy a first plurality of reference samples in the search window from the second memory to the first memory and (iii) map a plurality of reads from the first memory for a plurality of pad samples to the reference samples in the first memory, where the pad samples are determined to be outside the boundary.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.

Abstract: A plurality of memory circuits and a logic circuit. The plurality of memory circuits may be configured to store a plurality of pixels. The pixels may be used in a motion estimation stage of a video encoder. The logic circuit may be configured to (i) control which of the pixels are stored in which of the plurality of memory banks and (ii) control accessing of the plurality of pixels.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate an output signal and one or more motion vectors in response to (i) a bitstream signal and (ii) a predictor signal. The second circuit may be configured to generate one or more reference data pixels in response to an address signal and the output signal. The third circuit may be configured to generate the predictor signal and address signal in response to (i) the motion vectors and (ii) the reference data pixels.

Abstract: An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously. The second circuit may be configured to generate a plurality of sum values by adding the difference values. The third circuit may be configured to generate at least one motion vector in response to the sum values.

Abstract: An apparatus generally having a first circuit and a second circuit for motion estimation is disclosed. The first circuit may be configured to (i) generate a first motion vector for a block at an integer-pel resolution and (ii) determine a single block size associated with the first motion vector. The second circuit may be configured to (i) generate a plurality of second motion vectors at a sub-pel resolution by searching proximate the first motion vector using the single block size and (ii) determine a motion vector for the block as a particular one of the second motion vectors best matching a plurality of reference samples.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.

Abstract: A circuit generally comprising a multiport memory, a direct memory access engine and a programmable gate array is disclosed. The direct memory access engine may be configured to transfer a first program to the multiport memory. The programmable gate array may be configured to (i) load the first program directly from the multiported memory to program a codec function and (ii) generate a video output signal by performing the codec function on a video input signal using video data exchanged with the multiport memory.

Abstract: An apparatus comprising a first processing circuit and a second processing circuit. The first processing circuit may be configured to generate a motion vector residual in response to one or more macroblocks of an input signal. The second processing circuit may be configured to convert between (i) the motion vector residual and (ii) a binarized representation of the motion vector residual. The binarized representation of the motion vector residual generally comprises (i) a binarized representation of an absolute value of the motion vector residual and (ii) a binarized representation of a sign of the motion vector residual when the motion vector residual has a non-zero value. The binarized representation of the sign is generally located after an end of the binarized representation of the absolute value of the motion vector residual.

Abstract: An apparatus comprising a first circuit, a second circuit and an output circuit. The first circuit may be configured to generate (i) one of a first set of entropy coded input signals or a second set of entropy coded input signals and (ii) a data path signal. The second circuit may be configured to generate (i) a first set of entropy encoded output signals in response to decoding the second set of entropy coded input signals, or (ii) a second set of entropy coded output signals in response to decoding the first set of entropy coded input signals. The second circuit may provide real time decoding and encoding on a macroblock basis. The output circuit may be configured to present an output signal in response to (i) one of the first set of entropy coded output signals or the second set of entropy coded output signals and (ii) the data path signal.

Abstract: A method for decoding an input bitstream is disclosed. The method generally includes the steps of (A) generating an intermediate bitstream having an intermediate encoded format by converting the input bitstream having an input encoded format and an input order, (B) storing the intermediate bitstream in the input order and (C) generating an output signal having an output order by decoding the intermediate bitstream.

Abstract: A method for decoding an input bitstream is disclosed. The method generally includes the steps of (A) generating an intermediate bitstream having an intermediate encoded format by converting the input bitstream having an input encoded format and an input order, (B) storing the intermediate bitstream in the input order and (C) generating an output signal having an output order by decoding the intermediate bitstream.

Abstract: A circuit generally comprising a multiport memory, a direct memory access engine and a programmable gate array is disclosed. The direct memory access engine may be configured to transfer a first program to the multiport memory. The programmable gate array may be configured to (i) load the first program directly from the multiported memory to program a codec function and (ii) generate a video output signal by performing the codec function on a video input signal using video data exchanged with the multiport memory.

Abstract: An overlap processor receives and temporarily stores a plurality of aligned scan lines. Each scan line is representative of a lane or zone of an image. The processor sequentially reads the plurality of scan lines and then synchronously and selectively outputs the scan lines producing an output comprising one scan line representative of one lane or zone plus a predetermined amount of scan line data from an adjacent lane or zone or both adjacent lanes or zones.

Abstract: A processor comprises a plurality of parallel channels having an upstream end and a downstream end, Each channel comprises a video data bus for continuously transferring video data from the upstream end to the downstream end, a plurality of modules serially connected along the video data bus and a host computer connected to the downstream end of the plurality of channels for receiving the video data. Each module comprises a crossbar switch, a pixel processing element connected to the crossbar switch, a delay resource connected across the crossbar switch and a microprocessor operably integrated within each module for controlling the operation thereof. The microprocessors of each module are serially connected together for transmitting and undertaking commands. The host computer is also connected to the microprocessor of each module for issuing commands for controlling the operation of the processor.