Patents by Inventor Eric Carman
Eric Carman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230395131Abstract: Sense amplifiers for memory devices include latch transistors that are used to latch values based on charges in memory cells. A first latch transistor applies a reference voltage to a first gut node of the sense amplifier via one of these latch transistors. The sense amplifier also applies a charge to a second gut node from a memory cell corresponding to the sense amplifier. The sense amplifier also latches a value in the sense amplifier based on a relationship between the reference voltage and the charge.Type: ApplicationFiled: July 8, 2022Publication date: December 7, 2023Inventor: Eric Carman
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Publication number: 20230352080Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.Type: ApplicationFiled: June 30, 2023Publication date: November 2, 2023Inventors: Eric Carman, Daniele Vimercati
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Patent number: 11727981Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.Type: GrantFiled: July 7, 2021Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Eric Carman, Daniele Vimercati
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Patent number: 11574665Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.Type: GrantFiled: September 3, 2021Date of Patent: February 7, 2023Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Publication number: 20230011345Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.Type: ApplicationFiled: July 7, 2021Publication date: January 12, 2023Inventors: Eric Carman, Daniele Vimercati
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Publication number: 20210398576Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.Type: ApplicationFiled: September 3, 2021Publication date: December 23, 2021Inventor: Eric Carman
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Patent number: 11127443Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.Type: GrantFiled: January 8, 2020Date of Patent: September 21, 2021Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Publication number: 20210210126Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventor: Eric Carman
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Patent number: 10403349Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.Type: GrantFiled: September 24, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Patent number: 10402048Abstract: System and method for preventing undesirable smart device communications. A system includes memory for storing a list of contacts, the memory integrated into a smart device; and a locking application configured to permit a user to select and lock one or more contacts included within said list of contacts such that the user is unable to communicate with the selected one or more contacts via said smart device. The locking application may be further configured to permit a user to select a pre-established time period during which the one or more selected contacts remain locked. Challenges may be presented to the user to unlock the contacts in advance of the lockout time expiring. Optional features include GPS tracking, rewards, ride and networking modules.Type: GrantFiled: October 8, 2015Date of Patent: September 3, 2019Assignee: Colossus Mobile Applications LLCInventor: Eric Carman
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Publication number: 20190027203Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Inventor: Eric Carman
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Patent number: 10083733Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.Type: GrantFiled: August 29, 2017Date of Patent: September 25, 2018Assignee: MICRON TECHNOLOGY, INC.Inventor: Eric Carman
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Publication number: 20180005683Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.Type: ApplicationFiled: August 29, 2017Publication date: January 4, 2018Inventor: Eric Carman
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Publication number: 20170270992Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.Type: ApplicationFiled: March 16, 2016Publication date: September 21, 2017Inventor: Eric Carman
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Patent number: 9767880Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.Type: GrantFiled: March 16, 2016Date of Patent: September 19, 2017Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Patent number: 9679612Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.Type: GrantFiled: July 1, 2015Date of Patent: June 13, 2017Assignee: MICRON TECHNOLOGY, INC.Inventor: Eric Carman
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Publication number: 20150302898Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.Type: ApplicationFiled: July 1, 2015Publication date: October 22, 2015Applicant: MICRON TECHNOLOGY, INC.Inventor: Eric Carman
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Patent number: 9123410Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.Type: GrantFiled: August 27, 2013Date of Patent: September 1, 2015Assignee: Intel CorporationInventors: Hernan A. Castro, Jeremy M. Hirst, Eric Carman
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Patent number: 9076543Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.Type: GrantFiled: February 1, 2010Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Publication number: 20150063021Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.Type: ApplicationFiled: August 27, 2013Publication date: March 5, 2015Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric Carman