Abstract: Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

Abstract: Techniques and configurations for electronic memory are described. An apparatus may include a first set of memory cells coupled with a first plate line and a word line, where a memory cell in the first set of memory cells may be coupled with a first bit line, and a second set of memory cells coupled with a second plate line and the word line, where a memory cell of the second set of memory cells may be coupled with a second bit line. The apparatus may also include a sense component having a first node coupled with the first bit line and a first capacitor and a second node coupled with the second bit line and a second capacitor. Also, a set of capacitors may be coupled with both nodes. The capacitors may support adjustment of the voltage of the nodes of the sense component.

Abstract: Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

Abstract: Systems, methods, and apparatus are provided for discharging an access device in a memory device. An example structure includes a memory device having a local sense line and a bleeder device coupled to the local sense line and a bleeder supply. The memory device can also include a sense line multiplexor coupled to the local sense line and a global sense line, and a sense amplifier coupled to the global sense line. The sense amplifier can be configured to sense and latch a voltage of the global sense line in response to the memory device receiving a command. The memory device can further include a plurality of access devices coupled to the local sense line, a plurality of capacitors coupled to the plurality of access devices, and a plate voltage supply, separate from the bleeder supply, coupled to the plurality of capacitors.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Sense amplifiers for memory devices include latch transistors that are used to latch values based on charges in memory cells. A first latch transistor applies a reference voltage to a first gut node of the sense amplifier via one of these latch transistors. The sense amplifier also applies a charge to a second gut node from a memory cell corresponding to the sense amplifier. The sense amplifier also latches a value in the sense amplifier based on a relationship between the reference voltage and the charge.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Techniques and configurations for electronic memory are described. An apparatus may include a first set of memory cells coupled with a first plate line and a word line, where a memory cell in the first set of memory cells may be coupled with a first bit line, and a second set of memory cells coupled with a second plate line and the word line, where a memory cell of the second set of memory cells may be coupled with a second bit line. The apparatus may also include a sense component having a first node coupled with the first bit line and a first capacitor and a second node coupled with the second bit line and a second capacitor. Also, a set of capacitors may be coupled with both nodes. The capacitors may support adjustment of the voltage of the nodes of the sense component.

Abstract: Sense amplifiers for memory devices include latch transistors that are used to latch values based on charges in memory cells. A first latch transistor applies a reference voltage to a first gut node of the sense amplifier via one of these latch transistors. The sense amplifier also applies a charge to a second gut node from a memory cell corresponding to the sense amplifier. The sense amplifier also latches a value in the sense amplifier based on a relationship between the reference voltage and the charge.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

Abstract: System and method for preventing undesirable smart device communications. A system includes memory for storing a list of contacts, the memory integrated into a smart device; and a locking application configured to permit a user to select and lock one or more contacts included within said list of contacts such that the user is unable to communicate with the selected one or more contacts via said smart device. The locking application may be further configured to permit a user to select a pre-established time period during which the one or more selected contacts remain locked. Challenges may be presented to the user to unlock the contacts in advance of the lockout time expiring. Optional features include GPS tracking, rewards, ride and networking modules.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.