Patents by Inventor Eric Carman

Eric Carman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403349
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Patent number: 10402048
    Abstract: System and method for preventing undesirable smart device communications. A system includes memory for storing a list of contacts, the memory integrated into a smart device; and a locking application configured to permit a user to select and lock one or more contacts included within said list of contacts such that the user is unable to communicate with the selected one or more contacts via said smart device. The locking application may be further configured to permit a user to select a pre-established time period during which the one or more selected contacts remain locked. Challenges may be presented to the user to unlock the contacts in advance of the lockout time expiring. Optional features include GPS tracking, rewards, ride and networking modules.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 3, 2019
    Assignee: Colossus Mobile Applications LLC
    Inventor: Eric Carman
  • Publication number: 20190027203
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
    Type: Application
    Filed: September 24, 2018
    Publication date: January 24, 2019
    Inventor: Eric Carman
  • Patent number: 10083733
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Eric Carman
  • Publication number: 20180005683
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
    Type: Application
    Filed: August 29, 2017
    Publication date: January 4, 2018
    Inventor: Eric Carman
  • Publication number: 20170270992
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
    Type: Application
    Filed: March 16, 2016
    Publication date: September 21, 2017
    Inventor: Eric Carman
  • Patent number: 9767880
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Patent number: 9679612
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: June 13, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Eric Carman
  • Publication number: 20150302898
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.
    Type: Application
    Filed: July 1, 2015
    Publication date: October 22, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Eric Carman
  • Patent number: 9123410
    Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric Carman
  • Patent number: 9076543
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Publication number: 20150063021
    Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric Carman
  • Patent number: 8797819
    Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin
  • Publication number: 20130250674
    Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
    Type: Application
    Filed: May 21, 2013
    Publication date: September 26, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Eric CARMAN, Mikhail NAGOGA, Serguei OKHONIN
  • Patent number: 8446794
    Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 21, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin
  • Patent number: 8411513
    Abstract: Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit lines coupled directly to the plurality of memory cells. The semiconductor memory device may also include a multiplexer coupled to the plurality of local bit lines and a global bit line coupled to the multiplexer.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Patent number: 8411524
    Abstract: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Patent number: 8351266
    Abstract: Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device comprising applying a first voltage potential to a first region via a bit line, applying a second voltage potential to a second region of the memory device via a source line, applying a control voltage potential to a body region of the memory device via a word line that is spaced apart and capacitively coupled to the body region, and applying a third voltage potential to a third region of the memory device via a carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: January 8, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Patent number: 8315083
    Abstract: Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: November 20, 2012
    Assignee: Micron Technology Inc.
    Inventors: Ping Wang, Eric Carman
  • Publication number: 20120236671
    Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
    Type: Application
    Filed: May 23, 2012
    Publication date: September 20, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Eric CARMAN, Mikhail NAGOGA, Serguei OKHONIN