Patents by Inventor Eric Carman
Eric Carman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8797819Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: GrantFiled: May 21, 2013Date of Patent: August 5, 2014Assignee: Micron Technology, Inc.Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin
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Publication number: 20130250674Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: ApplicationFiled: May 21, 2013Publication date: September 26, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric CARMAN, Mikhail NAGOGA, Serguei OKHONIN
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Patent number: 8446794Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: GrantFiled: May 23, 2012Date of Patent: May 21, 2013Assignee: Micron Technology, Inc.Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin
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Patent number: 8411524Abstract: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array.Type: GrantFiled: January 5, 2011Date of Patent: April 2, 2013Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Patent number: 8411513Abstract: Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit lines coupled directly to the plurality of memory cells. The semiconductor memory device may also include a multiplexer coupled to the plurality of local bit lines and a global bit line coupled to the multiplexer.Type: GrantFiled: December 21, 2010Date of Patent: April 2, 2013Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Patent number: 8351266Abstract: Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device comprising applying a first voltage potential to a first region via a bit line, applying a second voltage potential to a second region of the memory device via a source line, applying a control voltage potential to a body region of the memory device via a word line that is spaced apart and capacitively coupled to the body region, and applying a third voltage potential to a third region of the memory device via a carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations.Type: GrantFiled: March 20, 2012Date of Patent: January 8, 2013Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Patent number: 8315083Abstract: Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region.Type: GrantFiled: April 22, 2011Date of Patent: November 20, 2012Assignee: Micron Technology Inc.Inventors: Ping Wang, Eric Carman
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Publication number: 20120236671Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: ApplicationFiled: May 23, 2012Publication date: September 20, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric CARMAN, Mikhail NAGOGA, Serguei OKHONIN
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Publication number: 20120176845Abstract: Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device comprising applying a first voltage potential to a first region via a bit line, applying a second voltage potential to a second region of the memory device via a source line, applying a control voltage potential to a body region of the memory device via a word line that is spaced apart and capacitively coupled to the body region, and applying a third voltage potential to a third region of the memory device via a carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations.Type: ApplicationFiled: March 20, 2012Publication date: July 12, 2012Applicant: MICRON TECHNOLOGY, INC.Inventor: Eric CARMAN
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Patent number: 8213226Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion, wherein the source and drain regions are opposing.Type: GrantFiled: December 7, 2009Date of Patent: July 3, 2012Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Patent number: 8194487Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: GrantFiled: September 17, 2008Date of Patent: June 5, 2012Assignee: Micron Technology, Inc.Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin
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Patent number: 8139418Abstract: Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first region via a bit line and applying a second voltage potential to a second region of the memory device via a source line. The method may also comprise applying a control voltage potential to a body region of the memory device via a word line that is spaced apart and capacitively coupled to the body region, wherein the body region is electrically floating and disposed between the first region and the second region. The method may further comprise applying a third voltage potential to a third region of the memory device via a carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations.Type: GrantFiled: March 16, 2010Date of Patent: March 20, 2012Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Patent number: 8134867Abstract: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array.Type: GrantFiled: May 9, 2011Date of Patent: March 13, 2012Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Publication number: 20110273942Abstract: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array.Type: ApplicationFiled: May 9, 2011Publication date: November 10, 2011Applicant: Micron Technology, Inc.Inventor: Eric CARMAN
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Publication number: 20110273947Abstract: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array.Type: ApplicationFiled: January 5, 2011Publication date: November 10, 2011Applicant: Innovative Silicon ISi SAInventor: Eric CARMAN
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Publication number: 20110228617Abstract: Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region.Type: ApplicationFiled: April 22, 2011Publication date: September 22, 2011Applicant: Micron Technology, Inc.Inventors: Ping Wang, Eric Carman
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Publication number: 20110216605Abstract: Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit lines coupled directly to the plurality of memory cells. The semiconductor memory device may also include a multiplexer coupled to the plurality of local bit lines and a global bit line coupled to the multiplexer.Type: ApplicationFiled: December 21, 2010Publication date: September 8, 2011Applicant: Innovative Silicon ISi SAInventor: Eric Carman
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Publication number: 20110199848Abstract: Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns.Type: ApplicationFiled: December 29, 2010Publication date: August 18, 2011Applicant: Innovative Silicon ISi SAInventors: Eric Carman, Philippe Bruno Bauser, Jean-Michel Daga
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Patent number: 7940559Abstract: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array.Type: GrantFiled: February 13, 2009Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventor: Eric Carman
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Patent number: 7933140Abstract: Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region.Type: GrantFiled: October 2, 2008Date of Patent: April 26, 2011Assignee: Micron Technology, Inc.Inventors: Ping Wang, Eric Carman