Patents by Inventor Eric D. Perfecto
Eric D. Perfecto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10041183Abstract: Disclosed are electrodeposition systems and methods wherein at least three electrodes are placed in a container containing a plating solution. The electrodes are connected to a polarity-switching unit and include a first electrode, a second electrode and a third electrode. The polarity-switching unit establishes a constant polarity state between the first and second electrodes in the solution during an active plating mode, wherein the first electrode has a negative polarity and the second electrode has a positive polarity, thereby allowing a plated layer to form on a workpiece at the first electrode. The polarity-switching unit further establishes an oscillating polarity state between the second and third electrodes during a non-plating mode (i.e.Type: GrantFiled: April 10, 2017Date of Patent: August 7, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto
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Patent number: 10002835Abstract: A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.Type: GrantFiled: February 8, 2017Date of Patent: June 19, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Benjamin V. Fasano, Michael S. Cranmer, Richard F. Indyk, Harry Cox, Katsuyuki Sakuma, Eric D. Perfecto
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Publication number: 20180166356Abstract: Various embodiments include integrated circuit (IC) package structures. In some cases, an IC package includes: a carrier having a recess; a plurality of IC chips coupled with the carrier inside the recess, the plurality of IC chips each including a plurality of connectors; a thermally conductive material between the plurality of IC chips and the carrier within the recess, the thermally conductive material coupling the plurality of IC chips with the carrier; a dielectric layer contacting the plurality of IC chips and the carrier; a redistribution layer (RDL) contacting the dielectric layer and the plurality of connectors, the RDL including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent IC chips in the plurality of IC chips; and a set of solder balls contacting the RDL and connected with the plurality of fan-out vias.Type: ApplicationFiled: December 13, 2016Publication date: June 14, 2018Inventors: Shahid A. Butt, Koushik Ramachandran, Eric D. Perfecto
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Patent number: 9853006Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.Type: GrantFiled: June 24, 2016Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
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Patent number: 9728440Abstract: A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.Type: GrantFiled: October 28, 2014Date of Patent: August 8, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Jorge A. Lubguban, Eric D. Perfecto, Jennifer D. Schuler
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Publication number: 20170211199Abstract: Disclosed are electrodeposition systems and methods wherein at least three electrodes are placed in a container containing a plating solution. The electrodes are connected to a polarity-switching unit and include a first electrode, a second electrode and a third electrode. The polarity-switching unit establishes a constant polarity state between the first and second electrodes in the solution during an active plating mode, wherein the first electrode has a negative polarity and the second electrode has a positive polarity, thereby allowing a plated layer to form on a workpiece at the first electrode. The polarity-switching unit further establishes an oscillating polarity state between the second and third electrodes during a non-plating mode (i.e.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Applicant: GlobalFoundries Inc.Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto
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Patent number: 9689084Abstract: Disclosed are electrodeposition systems and methods wherein at least three electrodes are placed in a container containing a plating solution. The electrodes are connected to a polarity-switching unit and include a first electrode, a second electrode and a third electrode. The polarity-switching unit establishes a constant polarity state between the first and second electrodes in the solution during an active plating mode, wherein the first electrode has a negative polarity and the second electrode has a positive polarity, thereby allowing a plated layer to form on a workpiece at the first electrode. The polarity-switching unit further establishes an oscillating polarity state between the second and third electrodes during a non-plating mode (i.e.Type: GrantFiled: May 22, 2014Date of Patent: June 27, 2017Assignee: GLOBALFOUNRIES INC.Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto
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Publication number: 20170148737Abstract: An interposer structure and a method of interconnecting first and second semiconductor dies are provided. A splice interposer is attached to a top surface of a substrate through a first plurality of pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through a second plurality of pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through a third plurality of pillars formed on the bottom surface of the first semiconductor. The height of the second plurality of pillars is greater than the height of the third plurality of pillars. The second semiconductor die is attached to the top surface of the splice interposer through a fourth plurality of pillars formed on a bottom surface of the second semiconductor die.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Benjamin V. FASANO, Michael S. CRANMER, Richard F. INDYK, Harry COX, Katsuyuki SAKUMA, Eric D. PERFECTO
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Patent number: 9607973Abstract: A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.Type: GrantFiled: November 19, 2015Date of Patent: March 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Benjamin V. Fasano, Michael S. Cranmer, Richard F. Indyk, Harry Cox, Katsuyuki Sakuma, Eric D. Perfecto
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Patent number: 9576922Abstract: A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.Type: GrantFiled: May 4, 2015Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Thomas J. Brunschwiler, Eric D. Perfecto, Jonas Zuercher
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Publication number: 20160329289Abstract: A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.Type: ApplicationFiled: May 4, 2015Publication date: November 10, 2016Inventors: Thomas J. Brunschwiler, Eric D. Perfecto, Jonas Zuercher
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Publication number: 20160307860Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
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Patent number: 9396991Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.Type: GrantFiled: August 25, 2014Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
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Patent number: 9379007Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.Type: GrantFiled: May 1, 2013Date of Patent: June 28, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Charles L. Arvin, Kenneth Bird, Charles C. Goldsmith, Sung K. Kang, Minhua Lu, Clare J. McCarthy, Eric D. Perfecto, Srinivasa S. N. Reddy, Krystyna W. Semkow, Thomas A. Wassick
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Patent number: 9343420Abstract: Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving chip-package interaction reliability. Underfill can be directly applied to a wafer, enabling increased filler loadings. Passages formed in the underfill and/or solder resist coating expose electrically conductive pads or metal pillars. Such passages can be filled with molten solder to form the solder bumps.Type: GrantFiled: February 14, 2014Date of Patent: May 17, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Brian M. Erwin, Eric D. Perfecto, Nicholas A. Polomoff, Jae-Woong Nah
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Publication number: 20160118287Abstract: A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.Type: ApplicationFiled: October 28, 2014Publication date: April 28, 2016Inventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Jorge A. Lubguban, Eric D. Perfecto, Jennifer D. Schuler
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Patent number: 9324669Abstract: A method including forming a copper pillar, electroplating a metal layer on a top surface and a sidewall of the copper pillar, and electroplating a metal cap above the top surface of the copper pillar in direct contact with the metal layer. The method further including forming an intermetallic by heating the metal layer and the copper pillar in a non-reducing environment, the intermetallic including elements of both the copper pillar and the metal layer, where molten solder will wet to the metal cap and will not wet to the intermetallic.Type: GrantFiled: September 12, 2014Date of Patent: April 26, 2016Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian M. Erwin, Eric D. Perfecto, Wolfgang Sauter
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Publication number: 20160079193Abstract: A method including forming a copper pillar, electroplating a metal layer on a top surface and a sidewall of the copper pillar, and electroplating a metal cap above the top surface of the copper pillar in direct contact with the metal layer. The method further including forming an intermetallic by heating the metal layer and the copper pillar in a non-reducing environment, the intermetallic including elements of both the copper pillar and the metal layer, where molten solder will wet to the metal cap and will not wet to the intermetallic.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Charles L. Arvin, Brian M. Erwin, Eric D. Perfecto, Wolfgang Sauter
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Publication number: 20160056072Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.Type: ApplicationFiled: August 25, 2014Publication date: February 25, 2016Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
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Publication number: 20150337451Abstract: Disclosed are electrodeposition systems and methods wherein at least three electrodes are placed in a container containing a plating solution. The electrodes are connected to a polarity-switching unit and include a first electrode, a second electrode and a third electrode. The polarity-switching unit establishes a constant polarity state between the first and second electrodes in the solution during an active plating mode, wherein the first electrode has a negative polarity and the second electrode has a positive polarity, thereby allowing a plated layer to form on a workpiece at the first electrode. The polarity-switching unit further establishes an oscillating polarity state between the second and third electrodes during a non-plating mode (i.e.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Applicant: International Business Machines CorporationInventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto