Abstract: A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.

Abstract: The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

Abstract: The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

Abstract: A process for transferring a thin film wiring layer to a substrate in the construction of multilayer chip modules initially provides a sacrificial release layer formed on a surface of a carrier. Directly on the release layer there is formed in inverted fashion a plurality of multilevel thin film structures having at least one wiring path of metallic material exposed on the surface opposite the carrier. An electronic packaging substrate is provided, and solder or other joining material is applied to one or both of the exposed metallic surface of the multilevel thin film structure or the substrate. The multilevel thin film structure is then joined to the substrate so that the attached carrier is remote from the substrate. The release layer is subsequently contacted with an etchant for the release layer so as to remove the carrier from the multilevel thin film structure to produce a multilayer chip module.

Abstract: A ceramic substrate pad used for establishing brazed connection between a pin and the substrate in the packaging of microelectronic semiconductor circuit chip. The pad is characterized by a stepped setback in the upper surface thereof which setback is oxidized to prevent wetting by the brazing alloy which bonds the pin to the pad. Stresses attributable to the brazing are isolated from the setback area and thus have reduced effect in causing cracking at the edges of the pad-substrate interface.

Abstract: A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Abstract: An electrical interconnect structure for connecting a substrate to the next level of packaging or to a semiconductor device. The interconnect structure includes at least two layers of polymeric material, one of the layers having a capture pad and the second of the layers having a bonding pad electrically connected to the capture pad. The bonding pad and the second layer of polymeric material are at the same height so that the bonding pad is level with the second layer of polymeric material. Finally, there is a cap of electrically conducting metallization on the bonding pad and extending beyond the second layer of polymeric material. The cap is of a different composition than the bonding pad.

Abstract: The present invention relates to an improved process for forming negative tone images of photosensitive polyimides on a substrate having improved wall angles.

Abstract: Standard processing techniques for creating a patterned polyimide film from a radiation sensitive polyimide film forming composition are modified to include a post-develop, flood exposure/hardening step which crosslinks precursors of the polyimide film prior to curing. The flood exposure/hardening step prevents pull-back of the wall profile which occurs during the shrinkage of radiation sensitive polyimide film forming composition which occurs during thermal curing.