Abstract: A multi-axis robot for high-speed applications comprises a first and a second guide rail arranged substantially parallel to each other for defining a first axis of motion. A crossbar having a first end and a second end is moveably supported on the guide rails. A carriage is moveably coupled to the crossbar for moving along a second axis of motion. A first drive system having first and second drives and a first belt running along a first H-shaped belt path provides for a movement of the carriage along the first and second axis of motion. Second and third belts extend at least partially along the crossbar and the guide rails. The second and third belts run along different second and third belt paths, with one of the second and third belts entering the crossbar with a right-hand turn and leaving the crossbar with a left-hand turn, and the other one of the second and third belts entering the crossbar with a left-hand turn and leaving the crossbar with a right-hand turn.

Abstract: The invention presents a programmable communication system for generating data for at least one processing unit at a fixed symbol frequency, which lies within a range of frequencies, on the basis of input samples received at an input frequency higher than the symbol frequency. To achieve this, communication time slots are reserved periodically as a function of the maximum envisaged symbol frequency, and the device is designed for using only a fraction of these slots reserved as a function of the fixed symbol frequency for transmitting the generated data. The invention is applicable to broadband digital communications, digital television, channel decoding, demodulation and other similar technology areas.

Abstract: The invention offers a method of calculating digital filters enabling to multiplex various different filters with the aid of a programmable co-processor circuit comprising a calculation element and memory registers. The invention comprises making an anticipated calculation of part of the result of the current filter before the last data included in the calculation of this result has arrived. For this purpose, successive products between predetermined filter coefficients and the corresponding input data which have already been used for the calculation of the preceding results are accumulated in an iterative fashion in an intermediate result in order to anticipate the calculation of the current result. The calculation of the last intermediate result for each final result is triggered each time a new input data is received, so that each filter result is immediately available once the last input data involved in this result has been received.

Abstract: A device provides a normally static and nevertheless programmable architecture, for example, a programmable digital demodulator. The device includes a first and a second processor module. The second module receives data and instructions and executes operations for obtaining a result. The first module transmits instructions to the second module according to a predetermined scheme, each instruction indicating the operation it is provided to execute in the current time slot. An operation is only executed by the second module if the necessary data are available. It is not possible to execute a different operation from the one that is provided in the current time slot. Thus, no result can be delivered outside the time slots provided for this purpose.

Abstract: The invention provides a programmable network architecture for interconnecting several calculation modules in a receiver of a data transmission system with a very high data rate, which receiver comprises a forward and a return communication path. The architecture renders it possible to realize local communications between neighboring calculation modules and global communications between non-neighboring calculation modules. The network is formed by a sequence of programmable interconnection cells comprising memory means for storing the data which traverse between two non-neighboring modules which are present in the forward path and the return path, respectively. The role of these memories is to guarantee that the data pass through at most two successive multiplexers in one clock cycle, so that a high clock speed can be chosen.

Abstract: The invention relates to a processing device for digital data which is capable of processing data which have been sampled with a sampling clock which may have any value whatsoever with respect to the basic clock of the device. To achieve this, the device is provided with means for generating from its basic clock an operational clock which is a function of the sampling clock of the data to be processed. This operational clock has a constant integer number of active periods during one cycle of the sampling clock. Application: Digital communication systems, especially demodulation.

Abstract: The invention relates to a digital demodulator whose architecture is adapted to multicarrier modulations (radio wave transmissions), but which remains suitable for use for monocarrier modulations (cable and satellite transmissions). With multicarrier modulations, the demodulator must carry out certain functions at a frequency of the order of sampling frequency and other functions at a frequency of the order of the symbol frequency. The invention comprises a separation of the architecture into three modules: a first module which carries out programs which are repeated with a first frequency, a second module capable of using programs which are repeated with a second frequency, and an interface module between the first and the second module. An advantage is that the memory size necessary for storing instructions for the first module is reduced. An application is for DVB standard transmission of digital TV programs.

Abstract: The present invention relates to a packaged product comprising flexible liquid-filled pouches and an outer container for containing the liquid-filled pouches; wherein the outer container contains a plurality of flexible liquid-filled pouches whereby at least two or more of the flexible liquid-filled pouches are in mutual contact, and in that the outer container further comprises means for avoiding or minimizing rupture of the flexible liquid-filled pouches when the outer container is subject to shock.

Abstract: The invention relates to a device (FFTP) for computing discrete transforms. The device comprises a local memory (RAM2) for registering results of sub-transform computations, a sub-transform computation comprising several computation layers. The device is characterized by computation means (CAL_M) which are capable of interlacing computation layers of two or several consecutive sub-transforms of the same size.

Abstract: The invention relates to a device which comprises a first and a second processor module. The second module M2 is intended to receive data and instructions and to execute operations for obtaining a result. The first module is intended to transmit instructions to the second module according to a predetermined scheme, each instruction indicating the operation it is provided to execute in the current time slot.

Abstract: A memory system is disclosed. The memory system provides for input data (datain_B and datain_F) and for taps (w_in) and is partitioned into various segments. The memory system includes means for recombining the segments in order to be adapted to different filters. In one embodiment, with the total dimension of the memory being 2L, the memory system includes six partitions having respective dimensions 2L/5, 4L/15, L/3, L/5, 2L/15, 2L/3, between which the data and taps are distributed by means of multiplexers.

Abstract: An apparatus having plurality of filter processing elements is provided in order to obtain adequate calculation power, particularly to enable a plurality of filters to be calculated by multiplexing. The calculation of a filter is effected in a plurality of iterations; a filter section is calculated in each iteration while the same operator is used for iteratively calculating a plurality of operations and a plurality of multiplexed filters; in each iteration a plurality of data sets is used. Each filter processing element comprises a number of partial-result registers (y-data) equal to the number of filters that can be multiplexed. Each register has a write input connected to the output (y) of a final adder and each register has a read output connected to one of the inputs (y-old) of the final adder.