Patents by Inventor Eric GRAETZ

Eric GRAETZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343094
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Applicant: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 10741402
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Publication number: 20180082848
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 22, 2018
    Applicant: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 9658279
    Abstract: A power semiconductor device includes a semiconductor body. The semiconductor body includes an active semiconductor region and a perimeter semiconductor region surrounding the active semiconductor region. The active semiconductor region has an active surface area, and the perimeter semiconductor region has a perimeter surface area. The power semiconductor device further includes a test structure for contactless testing of the perimeter semiconductor region. The test structure includes an electrically conductive path mounted on the perimeter surface area. The test structure is configured to extract energy from a remotely generated electromagnetic radio frequency test field.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies AG
    Inventors: Eric Graetz, Hermann Bilban, Rudolf Pairleitner
  • Publication number: 20160124039
    Abstract: A power semiconductor device includes a semiconductor body. The semiconductor body includes an active semiconductor region and a perimeter semiconductor region surrounding the active semiconductor region. The active semiconductor region has an active surface area, and the perimeter semiconductor region has a perimeter surface area. The power semiconductor device further includes a test structure for contactless testing of the perimeter semiconductor region. The test structure includes an electrically conductive path mounted on the perimeter surface area. The test structure is configured to extract energy from a remotely generated electromagnetic radio frequency test field.
    Type: Application
    Filed: October 26, 2015
    Publication date: May 5, 2016
    Inventors: Eric Graetz, Hermann Bilban, Rudolf Pairleitner
  • Publication number: 20150262814
    Abstract: A power semiconductor device in accordance with various embodiments may include: a semiconductor body; and a passivation layer disposed over at least a portion of the semiconductor body, wherein the passivation layer includes an organic dielectric material having a water uptake of less than or equal to 0.5 wt % in saturation.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: Infineon Technologies AG
    Inventors: Mathias Plappert, Eric Graetz, Andreas Behrendt, Oliver Humbel, Carsten Schaeffer, Angelika Koprowski
  • Patent number: 8835978
    Abstract: Representative implementations of devices and techniques provide a high-voltage device on a semiconductor substrate. An insulating polymer layer is formed on an opposite surface to the high-voltage device, the insulating polymer layer having a thickness of at least twice that of the semiconductor substrate.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Eric Graetz
  • Publication number: 20140035094
    Abstract: One or more embodiments relate to a semiconductor structure, comprising: a silicon rubber layer; and a semiconductor layer overlying the silicon rubber layer.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 6, 2014
    Inventor: Eric GRAETZ
  • Publication number: 20130299871
    Abstract: Representative implementations of devices and techniques provide a high-voltage device on a semiconductor substrate. An insulating polymer layer is formed on an opposite surface to the high-voltage device, the insulating polymer layer having a thickness of at least twice that of the semiconductor substrate.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Inventors: Anton MAUDER, Eric GRAETZ
  • Patent number: 8518798
    Abstract: One or more embodiments relate to a method for forming a semiconductor structure, including: forming a semiconductor layer; and forming a dielectric layer over a back side of said semiconductor layer. In one or more embodiments, the dielectric layer may be a silicone rubber layer.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: August 27, 2013
    Assignee: Infineon Technologies AG
    Inventor: Eric Graetz
  • Publication number: 20120074517
    Abstract: One or more embodiments relate to a method for forming a semiconductor structure, including: forming a semiconductor layer; and forming a dielectric layer over a back side of said semiconductor layer. In one or more embodiments, the dielectric layer may be a silicone rubber layer.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Inventor: Eric GRAETZ