SEMICONDUCTOR STRUCTURE
One or more embodiments relate to a semiconductor structure, comprising: a silicon rubber layer; and a semiconductor layer overlying the silicon rubber layer.
The present application is a divisional application of U.S. patent application Ser. No. 12/888,454, filed on Sep. 23, 2010. U.S. patent application Ser. No. 12/888,454 is hereby incorporated by reference herein.
TECHNICAL FIELDOne or more embodiments of the present invention relate to semiconductor structures and methods for making semiconductor structures.
BACKGROUNDTo achieve faster switching lateral power semiconductor devices it may be useful to reduce the amount of mobile charge below the device. New device structures are needed.
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
In one or more embodiments, the support structure 210 may be a semiconductor substrate (e.g. a semiconductor wafer). In one or more embodiments, the semiconductor substrate may be a bulk semiconductor substrate (e.g. a bulk semiconductor wafer). In one or more embodiments, the semiconductor substrate may be an SOI semiconductor substrate (e.g. an SOI semiconductor wafer). An SOI semiconductor substrate may include a bulk semiconductor substrate, an SOI dielectric layer, and a semiconductor layer overlying the SOI dielectric layer.
In one or more embodiments, a semiconductor substrate may be a silicon substrate (e.g. a silicon wafer). The silicon substrate may be a bulk silicon substrate (e.g. a bulk silicon wafer) comprising monocrystalline silicon. Hence, in one or more embodiments, the bulk semiconductor substrate may be a bulk silicon substrate (e.g. bulk silicon wafer). The bulk silicon substrate may include or may not include an epitaxial layer.
An example of a bulk silicon substrate (e.g. a bulk silicon wafer) is a Czochralski (CZ) silicon wafer. Another type of a bulk silicon wafer is a Flat-Zone (FZ) silicon wafer. The bulk silicon substrate (e.g. bulk silicon wafer) may comprise (or may consist essentially of) bulk silicon such as bulk monocrystalline silicon. The bulk silicon may be p-doped.
In one or more embodiments, a silicon substrate may be an SOI silicon substrate. The SOI silicon substrate may include a bulk silicon substrate, an SOI dielectric layer and a layer of bulk silicon overlying said SOI dielectric layer. The SOI dielectric layer may be a buried oxide layer.
Other examples of semiconductor substrates include, but not limited to, silicon carbide substrates (e.g. wafers), GaAs substrates (e.g. wafers) and GaN substrates (e.g. wafers). A substrate may be a bulk substrate (e.g. bulk wafer) or a substrate may be an SOI substrate (e.g. SOI wafer). As noted, an SOI semiconductor substrate (e.g. an SOI semiconductor wafer) may include a bulk semiconductor substrate, a dielectric layer overlying the bulk semiconductor substrate and a semiconductor layer overlying the dielectric layer.
It is noted that an additional example of a semiconductor substrate (e.g. an SOI semiconductor substrate) is a SOS (silicon on sapphire) substrate.
As noted, in one or more embodiments, the support structure 210 may be a bulk semiconductor substrate 210 (However, it is understood that the support structure 210 may be any type of support structure including any type of semiconductor substrate). The substrate 210 has a front side 210F (e.g. top side) and a back side 210B (e.g. bottom side). Referring to
The etch stop layer 220 may be formed by an ion implantation process. In some embodiments, the ion implantation may be ion implantation of donors and/or acceptors. In some embodiments, the etch stop layer 220 may be formed by the ion implantation of germanium.
Referring to
Referring to
In one or more embodiments, the semiconductor layer 230 may be formed as an epitaxial layer. The semiconductor layer 230 (e.g. epitaxial layer) may, for example, be formed by an epitaxial growth process. In one or more embodiments, the epitaxial growth process may be a selective epitaxial growth process. In one or more embodiments, the epitaxial layer may be formed by using a deposition process such as a chemical vapor deposition process. In one or more embodiments, the substrate 210 may be a bulk silicon substrate (e.g. a bulk silicon wafer) and may comprise bulk silicon (such as bulk monocrystalline silicon). In this case, the semiconductor layer 230 (e.g. an epitaxial layer) may also include bulk silicon (for example, bulk monocrystalline silicon). In one or more embodiments, the epitaxial layer may be a bulk monocrystalline silicon layer. The monocrystalline silicon layer may be a doped layer. The dopant may be p-type or n-type.
The semiconductor layer 230 (e.g. the epitaxial layer) may be doped (e.g. p-type or n-type) by an in-situ process or by an introduction process such as ion implantation or diffusion. There may be other ways of introducing the dopant. In one or more embodiments, the dopant type of the semiconductor layer 230 may be the same as the dopant type of the bulk semiconductor substrate 210.
It is noted that the semiconductor layer 230 may include any semiconductor material and is not limited to silicon. The semiconductor layer may include one or more semiconductor materials. The semiconductor layer may include one or more semiconductor compounds. Examples of semiconductor materials include silicon, GaAs, GaN and combinations thereof. In one or more embodiments, the semiconductor layer 230 may be formed of the same semiconductor materials as the semiconductor substrate 210. In one or more embodiments, the semiconductor layer 230 may comprise one or more different semiconductor materials from the semiconductor substrate 210.
In one or more embodiments, the semiconductor layer 230 may be in direct contact with the substrate 210.
In some embodiments, the semiconductor layer 230 may have a thickness of about 20 microns or less. In some embodiments, the semiconductor layer 230 may have a thickness of about 15 microns or less. In some embodiments, the semiconductor layer 230 may have a thickness of about 10 microns or less. In one or more embodiments, the semiconductor layer 230 may have a thickness of about 5 microns or more.
Referring to
In one or more embodiments, the layer 240 may be in direct contact with the semiconductor layer 230.
Referring to
A device 245 may be any type of electronic device and/or semiconductor device. The device 245 may be an active device or a passive device. The device 245 may be formed so that at least a portion of the device may formed within the semiconductor layer 230 and/or at least a portion of the device may be formed over a front side 230F (e.g. top side) of the semiconductor layer 230. Hence, in one or more embodiments, a portion of a device 245 may be formed within the semiconductor layer and a portion of a device may be formed over the front side 230F of semiconductor layer 230. In one or more embodiments, a device may be formed so that essentially all of the device is formed within the semiconductor layer 230. In one or more embodiments, a device may be formed so that essentially all of the device is formed over the front side 230F of the semiconductor layer 230.
In one or more embodiments, the device 245 may include at least a portion of layer 240. In one or more embodiments, at least a portion of device 245 may be formed as a result of forming at least a portion of layer 240.
In one or more embodiments, the device 245 may, for example, be a transistor. In one or more embodiments, a transistor (e.g. MOS transistor) may be formed such that the source/drain regions are formed within the semiconductor layer 230. The gate of the transistor may be formed over the front side 230F of the semiconductor layer 230. In another embodiment, the device 245 may be a bipolar transistor. In some embodiments, the device 245 may be a lateral device. In some embodiments, a lateral device may be a device where the device current flows substantially perpendicular to the thickness of the semiconductor layer 230. An example of a lateral device is shown in
Referring to
The bulk semiconductor substrate 210 (which may, for example, be a bulk silicon substrate) may then be removed. This may be done in a single step or this may be done using two or more removal steps. Referring to
Hence, in an embodiment, the back side grinding process may thin the part 210R without completely removing it. In some embodiments, as a result of the back side grinding process, the thickness of the substrate 210 may be reduced to a thickness of about 40 microns or below. In some embodiments, the thickness of the substrate 210 may be reduced to a thickness of about 30 microns or below.
The result of the back side grinding process is shown in
Referring to
This second removal process (e.g. a wet etching process) may be continued until the etch stop layer 220 is reached or exposed. In some embodiments, the etching of the part 210R may stop essentially on the etch stop layer 220. It is possible that a small amount of the etch stop layer is also etched. Hence, in one or more embodiments, the etching process to remove a portion of part 210R may stop essentially on the etch stop layer 220. The result of the second removal process (e.g. the wet etching process) is shown in
Referring to
It is possible that the etch stop layer 220 may be formed slightly below the front side 210F of the bulk substrate 210. In this case, the etch used to remove the etch stop layer 220 (e.g. phosphoric acid) may also be used to etch (e.g. as an over etch) the small amount of (non-etch stop) substrate 210 that may be overlie the etch stop layer 220 and be between the etch stop layer 220 and the semiconductor layer 230.
The etching of the etch stop layer 220 may be performed as a controlled (e.g. timed) etch so that the etch may stop essentially when the semiconductor layer 230 (e.g. epitaxial layer) is reached. It is understood that, since the etch may be a timed etch, it is possible that a small amount of the semiconductor layer 230 may also be etched in the process of removing the etch stop layer 220. In some embodiments, removal of the etch stop layer 220, may thus complete the removal of the bulk semiconductor substrate 210. It is understood that, in some instances, it may be possible that a trace amount of the substrate 210 (or some other support structure) may remain.
It is noted, in some embodiments, it is possible that an etch stop layer 220 is not formed and that the semiconductor substrate 210 is removed without the use of an etch stop layer. Referring to
In one or more embodiments, the layer 260 may comprise (or may consist essentially of) silicone rubber. In one or more embodiments, the layer 260 may be a silicone rubber layer. The silicon rubber layer 260 may be applied by a spin coat process. The silicone rubber may be a polymer material. The polymer may, for example, be a polysiloxanes. The polysiloxanes may include a siloxane backbone consisting of Si—O—Si units.
In one or more embodiments, the layer 260 may have a thickness of about 25 microns or more. In one or more embodiments, the layer 260 may have a thickness of about microns or more. In one or more embodiments, the layer 260 may have a thickness of about 75 microns or more. In one or more embodiments, the layer 260 may have a thickness of about 100 microns or more. In one or more embodiments, the layer 260 may have a thickness of about 150 microns or less. In one or more embodiments, the layer 260 may have a thickness of about 125 microns or less. In one or more embodiments, the layer 260 may have a thickness of about 100 microns.
Referring to
The first bake process BAKE1 may be useful after the application of the silicone rubber layer 260. The first bake process may help to mechanically stabilize the silicone rubber layer and may prevent thickness variations or may help prevent the silicone rubber from dripping.
Referring to
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The semiconductor chip 300 may include at least one device 245 (e.g. an electronic device and/or semiconductor device). As noted above, the device 245 may be any device, including any passive or active device. In the embodiment shown in
Examples of the device 245 have been provided above. In some embodiments, the device 245 may be a lateral device. In some embodiments, a lateral device may be a device where the device current flows substantially perpendicular to the thickness of the semiconductor layer 230. The device current may, for example, be the channel current of a transistor (such as a MOS transistor). An example of a lateral device is a lateral DMOS transistor. Another example of a lateral device is an Insulated Gate Bipolar Transistor (IGBT).
An example of a lateral device is shown as device 245 in
In one or more embodiments, the device 245 shown in
Referring to
Hence, in the embodiment of
In one or more embodiments, the semiconductor layer 230 may be formed using certain techniques related to SOI semiconductor substrate (e.g. SOI semiconductor wafer) manufacturing. In one or more embodiments, the semiconductor layer 230 may be formed using a bonding (e.g. wafer bonding) method. In one or more embodiments, it may be possible that the semiconductor layer 230 be formed using a seed method.
It is noted that the semiconductor layer 230 may include any semiconductor material and is not limited to silicon. The semiconductor layer may include one or more semiconductor materials. The semiconductor layer may include one or more semiconductor compounds. Examples of semiconductor materials include silicon, GaAs, GaN and combinations thereof. In one or more embodiments, the semiconductor layer 230 may be formed of the same semiconductor materials as the semiconductor substrate 210. In one or more embodiments, the semiconductor layer 230 may comprise one or more different semiconductor materials from the semiconductor substrate 210.
Referring to
As noted above, a device 245 may be formed over the front side of semiconductor substrate 210. The device 245 may be formed at least partially within layer 230 and/or at least partially over the front side of layer 230.
Referring to
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In one or more embodiments, it may also possible that the protection structure 250 be removed at any time after the back side grinding of the semiconductor substrate 210. It may also be possible that a protection structure 250 is not used.
Referring again to
In some embodiments, the structure 510 may, in some embodiments, be replaced with an SOI semiconductor substrate (e.g. an SOI semiconductor wafer). The SOI substrate (e.g. SOI wafer) may be made or purchased.
In comparing the structure 510 shown in
As least a portion of the processing steps as depicted in FIGS. 18A,B through 27 may be formed on the SOI substrate (e.g. SOI wafer) 1510 shown in
In the embodiments shown in
However, in other embodiments, the bulk semiconductor substrate may be replaced with any other type of support structure. Hence, the support structure 210 may be any type of support structure. In one or more embodiments, the support structure may be any type of semiconductor substrate (e.g. a semiconductor wafer). In one or more embodiments, the semiconductor substrate may be a bulk semiconductor substrate (e.g. a bulk semiconductor wafer). In one or more embodiments, the semiconductor substrate may be an SOI semiconductor substrate (e.g. an SOI semiconductor wafer). In one or more embodiments, a semiconductor substrate may be a silicon substrate (e.g. a silicon wafer) such as a bulk silicon substrate (e.g. bulk silicon wafer) or an SOI silicon substrate (e.g. SOI silicon wafer).
In some embodiments, the support structure 210 (as shown, for example, in
In some embodiments, the support structure 210 may be a homogeneous layer. In some embodiments, the support structure may include a stack of a plurality of sub-layers of different materials. Hence, as noted, the support structure 210 shown in
A semiconductor layer 230 may be formed over the support structure 210 and the support structure 210 may then removed and replaced with a silicone rubber layer (or some other dielectric layer). Hence, the support structure 210 may be removed (possibly by mechanical and or chemical means) and replaced by the silicone rubber layer (or some other dielectric layer). In one or more embodiments, one or more electronic devices (or an integrated circuit) may be formed within and/or over front side of the semiconductor layer 230 prior to removal of the support structure 210. In one or more embodiments, it may be possible to form one or more electronic devices (or an integrated circuit) after the support structure 210 has been replaced with a silicone rubber layer (or other dielectric layer). In one or more embodiments, it may be possible to form one or more electronic devices (or an integrated circuit) after the support structure 210 has been removed but before it has been replaced with a silicone rubber layer (or other dielectric layer). In some embodiments, one or more etch stop layers may be formed within the support structure 210. In some embodiments, one or more etch stop layers may be formed over the support structure 210. In some embodiments, it may be possible that one or more etch stop layers be formed within the support structure and one or more etch stop layers be formed over the support structure.
In one or more embodiments, it is possible that the silicone rubber layer be replaced with a layer of a different material. In one or more embodiments, the different material may be a dielectric material. In one or more embodiments, the different material may remain stable (e.g. thermally and/or chemically stable) at a temperature of about 250° C.
One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a support structure; forming a semiconductor layer over the support structure; removing the support structure; and forming a dielectric layer over a back side of the semiconductor layer after removing the support structure. In one or more embodiments, the dielectric layer may be a silicone rubber layer.
One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a semiconductor layer over the semiconductor substrate; forming a device within the semiconductor layer and/or over a front side of the semiconductor layer; removing the semiconductor substrate; and forming a dielectric layer over a back side of the semiconductor layer after removing the bulk semiconductor substrate. In one or more embodiments, the dielectric layer may be a silicone rubber layer. In one or more embodiments, said semiconductor substrate may be a semiconductor wafer.
One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing an SOI semiconductor substrate, the SOI substrate including a bulk semiconductor substrate, a first dielectric layer overlying the bulk substrate and a semiconductor layer overlying the first dielectric layer; removing the bulk substrate; and forming a second dielectric layer over a back side of the semiconductor layer after removing the bulk substrate. In one or more embodiments, the second dielectric layer may be a silicone rubber layer.
One or more embodiments relate to a method for forming a semiconductor structure, comprising: forming a semiconductor layer; and forming a dielectric layer over a back side of the semiconductor layer.
One or more embodiments relate to a semiconductor structure, comprising: a silicone rubber layer; and a semiconductor layer overlying the silicone layer.
One or more embodiments relate to a semiconductor structure, comprising: a dielectric layer having a thickness of at least about 25 microns; and a semiconductor layer overlying the dielectric layer.
It is to be understood that the disclosure set forth herein is presented in the form of detailed embodiments described for the purpose of making a full and complete disclosure of the present invention, and that such details are not to be interpreted as limiting the true scope of this invention as set forth and defined in the appended claims.
Claims
1. A semiconductor structure, comprising:
- a silicone rubber layer; and
- a semiconductor layer overlying said silicone layer.
2. The structure of claim 1, wherein said semiconductor layer comprises monocrystalline silicon.
3. The structure of claim 1, further comprising a device, at least a portion of said device disposed within said semiconductor layer and/or at least a portion of said device disposed over said semiconductor layer.
4. The structure of claim 3, wherein said device is a lateral device.
5. The structure of claim 1, wherein said semiconductor layer is in direct contact with said silicone rubber layer.
6. A semiconductor structure, comprising:
- a dielectric layer having a thickness of at least about 25 microns; and
- a semiconductor layer overlying said dielectric layer.
7. The structure of claim 8, wherein said semiconductor layer comprises bulk moncrystalline silicon.
8. The structure of claim 8, further comprising a device, at least a portion of said device disposed within said semiconductor layer and/or at least a portion of said device disposed over a front side of said semiconductor layer.
9. The structure of claim 8, wherein said device is a lateral device.
10. The structure of claim 6, wherein said dielectric layer has a thickness of at least about 50 microns.
11. The structure of claim 6, wherein said dielectric layer is a solid material.
12. The structure of claim 6, wherein said semiconductor layer is in direct contact with said dielectric layer.
13. The structure of claim 6, wherein dielectric layer comprises silicon rubber.
Type: Application
Filed: Aug 22, 2013
Publication Date: Feb 6, 2014
Inventor: Eric GRAETZ (Krumpendorf)
Application Number: 13/972,964
International Classification: H01L 29/06 (20060101);