Patents by Inventor Eric Guiot

Eric Guiot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250233031
    Abstract: A substrate for a power or radiofrequency electronic device includes a self-supporting support substrate made of polycrystalline silicon carbide and a surface layer of monocrystalline silicon carbide that extends over a front face of the support substrate. The support substrate has at least one porous portion extending from a rear face of the support substrate. The porous portion has a degree of porosity of greater than 5%.
    Type: Application
    Filed: April 4, 2023
    Publication date: July 17, 2025
    Inventors: Hugo Biard, Damien Radisson, Eric Guiot
  • Patent number: 12270123
    Abstract: A method for producing a substrate for the epitaxial growth of a gallium-based III-N alloy layer comprises the following successive steps: —providing a donor substrate of single-crystal silicon carbide; —implanting ions in the donor substrate to form an embrittlement zone defining a thin film layer of single-crystal SiC; —bonding the donor substrate onto a first receiving substrate via a bonding layer; —detaching the donor substrate along the embrittlement zone to transfer the thin film of SiC onto the first receiving substrate; —epitaxially growing a layer of semi-insulating SiC having a thickness greater than 1 ?m on the thin film of SiC; —bonding the layer of semi-insulating SiC onto a second receiving substrate having a high electrical resistivity; —removing at least a portion of the bonding layer to detach the first receiving substrate; and —removing the transferred thin film of single-crystal SiC, to expose the semi-insulating SiC layer.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: April 8, 2025
    Assignee: Soitec
    Inventor: Eric Guiot
  • Publication number: 20250063784
    Abstract: A method of manufacturing a semiconductor structure, which includes a support substrate of polycrystalline silicon carbide and an active layer of single-crystal silicon carbide, involves: the formation of a support substrate including a stack of a first layer of polycrystalline SiC mainly of polytype 3C and of a second layer of polycrystalline SiC mainly of polytype 4H and/or 6H, the bonding of a donor substrate including an active layer of single-crystal SiC of polytype 4H or 6H to a face of polytype 4H and/or 6H of the support substrate, and the transfer of the active layer onto the support substrate.
    Type: Application
    Filed: December 13, 2022
    Publication date: February 20, 2025
    Inventors: Hugo Biard, Eric Guiot
  • Patent number: 12198983
    Abstract: A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: January 14, 2025
    Assignee: Soitec
    Inventors: Ionut Radu, Hugo Biard, Christophe Maleville, Eric Guiot, Didier Landru
  • Publication number: 20240271321
    Abstract: A method of fabricating a composite structure includes providing a c-SiC initial substrate, depositing a relatively thin p-SiC first layer on a front side of the initial substrate at a relatively high temperature, the first layer having a dopant concentration greater than 1019/cm3, forming a buried brittle plane in the initial substrate delineating a thin layer of single crystal SiC between the brittle plane and a front side of the initial substrate, depositing a relatively thick amorphous and/or polycrystalline SiC second layer on the first layer at a relatively low temperature, the second layer including dopants of the same type as those of the first layer, at a concentration greater than 1019/cm3, and depositing a p-SiC third layer on the second layer at a relatively high temperature. A separation along the buried brittle plane takes place during the deposition process.
    Type: Application
    Filed: September 13, 2022
    Publication date: August 15, 2024
    Inventors: Frédéric Allibert, Eric Guiot
  • Publication number: 20240266172
    Abstract: The invention relates to a semiconductor structure (100) that comprises a useful layer (10) made of monocrystalline semiconductor material and extending along a main plane (x, y), a support substrate (30) made of semiconductor material, and an interface area (20) between the useful layer (10) and the support substrate (30), the support substrate extending parallel to the main plane (x, y), the structure (100) being characterised in that the interface area (20) comprises nodules (21) that:—are electrically conductive, in that they contain a metal material forming ohmic contact with the useful layer (10) and the support substrate (30);—have a thickness, along an axis (z) normal to the main plane (x, y) , of less than or equal to 30 nm;—are separate or adjoining, the separate nodules (21) being separated from each other by regions (22) of direct contact between the useful layer (10) and the support substrate (30). The invention also relates to a method for manufacturing the structure (100).
    Type: Application
    Filed: June 8, 2021
    Publication date: August 8, 2024
    Inventors: Frédéric Allibert, Didier Landru, Oleg Kononchuk, Eric Guiot, Gweltaz Gaudin, Julie Widiez, Franck Fournel
  • Publication number: 20230411140
    Abstract: A method of producing a substrate for epitaxial growth of a gallium-based III-N alloy layer comprises the following consecutive steps: —providing a donor substrate of semi-insulating monocrystalline silicon carbide, —implanting ionic species in the donor substrate so as to form a zone of weakness defining a thin layer of semi-insulating monocrystalline SiC to be transferred, —bonding the donor substrate to a first receiving substrate by means of a bonding layer, —detaching the donor substrate along the zone of weakness so as to transfer the thin layer of semi-insulating monocrystalline SiC on to the first receiving substrate, —forming an additional layer of semi-insulating SiC on the transferred thin layer, —bonding the additional layer to a second receiving substrate having a high electrical resistivity, —removing at least a portion of the bonding layer so as to detach the first receiving substrate and expose the layer of transferred semi-insulating monocrystalline SiC.
    Type: Application
    Filed: October 4, 2021
    Publication date: December 21, 2023
    Inventor: Eric Guiot
  • Publication number: 20230411151
    Abstract: A method of fabricating a substrate for epitaxial growth of a layer of gallium nitride (GaN), aluminum gallium nitride (AlGaN) or indium gallium nitride (InGaN), comprises the following successive steps: providing a base substrate comprising at least one layer of single-crystal silicon carbide, performing epitaxial growth of a layer of semi-insulating SiC having a thickness larger than 1 ?m on the layer of single-crystal SiC to form a donor substrate, implanting ionic species into the layer of semi-insulating SiC so as to form a weakened region defining a thin layer of single-crystal semi-insulating SiC to be transferred, bonding the layer of semi-insulating SiC directly to a receiver substrate having a high electrical resistivity, and detaching the donor substrate along the weakened region so as to transfer the thin layer of single-crystal semi-insulating SiC to the receiver substrate.
    Type: Application
    Filed: October 4, 2021
    Publication date: December 21, 2023
    Inventor: Eric Guiot
  • Publication number: 20230374701
    Abstract: A method for producing a substrate for the epitaxial growth of a gallium-based III-N alloy layer comprises the following successive steps: —providing a donor substrate of single-crystal silicon carbide; —implanting ions in the donor substrate to form an embrittlement zone defining a thin film layer of single-crystal SiC; —bonding the donor substrate onto a first receiving substrate via a bonding layer; —detaching the donor substrate along the embrittlement zone to transfer the thin film of SiC onto the first receiving substrate; —epitaxially growing a layer of semi-insulating SiC having a thickness greater than 1 ?m on the thin film of SiC; —bonding the layer of semi-insulating SiC onto a second receiving substrate having a high electrical resistivity; —removing at least a portion of the bonding layer to detach the first receiving substrate; and —removing the transferred thin film of single-crystal SiC, to expose the semi-insulating SiC layer.
    Type: Application
    Filed: October 4, 2021
    Publication date: November 23, 2023
    Inventor: Eric Guiot
  • Publication number: 20230260841
    Abstract: A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.
    Type: Application
    Filed: October 26, 2020
    Publication date: August 17, 2023
    Inventors: Ionut Radu, Hugo Biard, Christophe Maleville, Eric Guiot, Didier Landru
  • Patent number: 11251321
    Abstract: An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm·cm2, preferably less than 5 mOhm·cm2.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 15, 2022
    Assignees: Soitec, Commissariat A L'Energie Atomigue et aux Energies Alternatives
    Inventors: Eric Guiot, Aurelie Tauzin, Thomas Signamarcheix, Emmanuelle Lagoutte
  • Publication number: 20210193853
    Abstract: An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm·cm2, preferably less than 5 mOhm·cm2.
    Type: Application
    Filed: January 27, 2017
    Publication date: June 24, 2021
    Applicants: Soitec, Commissariat A L'Energie Atomique et aux Energies Alternatives, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Eric Guiot, Aurelie Tauzin, Thomas Signamarcheix, Emmanuelle Lagoutte
  • Patent number: 10361326
    Abstract: This disclosure relates to a solar cell assembly structure for supporting a concentrator photovoltaic cell comprising a semiconducting structure and a diode, wherein the semiconducting structure comprises a first semiconducting region at least a part of which for placing the concentrator photovoltaic cell structure, and a second semiconducting region for realizing the diode within or on the second semiconducting region and wherein the part of the first semiconducting region for placing the concentrator photovoltaic cell structure and the second semiconducting region are not vertically overlapping.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 23, 2019
    Assignee: Soitec
    Inventors: Cécile Aulnette, Rainer Krause, Frank Dimroth, Eric Guiot, Eric Mazaleyrat, Charlotte Drazek
  • Patent number: 9954139
    Abstract: This disclosure is related to a manufacturing method for a plurality of photovoltaic cells comprising the steps of: obtaining a plurality of photovoltaic cells placed at a first distance from each other; attaching a stretching material to the plurality of photovoltaic cells; and stretching the stretching material such that the plurality of photovoltaic cells result at a second distance from each other, wherein the second distance is greater that the first distance.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: April 24, 2018
    Assignee: SOITEC
    Inventors: Rainer Krause, Cecile Aulnette, Eric Mazaleyrat, Frank Dimroth, Eric Guiot
  • Publication number: 20160056318
    Abstract: This disclosure relates to a solar cell assembly structure for supporting a concentrator photovoltaic cell structure (3420), comprising a semiconducting structure and a diode, wherein the semiconducting structure comprises a first semiconducting region at least a part of which for placing the concentrator photovoltaic cell structure, and a second semiconducting region for realizing the diode within or on the second semiconducting region and wherein the part of the first semiconducting region for placing the concentrator photovoltaic cell structure and the second semiconducting region are not vertically overlapping.
    Type: Application
    Filed: March 26, 2014
    Publication date: February 25, 2016
    Inventors: Cecile Aulnette, Rainer Krause, Frank Dimroth, Matthias Grave, Eric Guiot, Eric Mazaleyrat, Charlotte Drazek
  • Publication number: 20160043254
    Abstract: This disclosure is related to a manufacturing method for a plurality of photovoltaic cells comprising the steps of: obtaining a plurality of photovoltaic cells placed at a first distance from each other; attaching a stretching material to the plurality of photovoltaic cells; and stretching the stretching material such that the plurality of photovoltaic cells result at a second distance from each other, wherein the second distance is greater that the first distance.
    Type: Application
    Filed: March 26, 2014
    Publication date: February 11, 2016
    Inventors: Rainer Krause, Cecile Aulnette, Eric Mazaleyrat, Frank Dimroth, Eric Guiot
  • Patent number: 9136113
    Abstract: A process for avoiding formation of an Si—SiO2—H2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si—SiO2—H2 environment on the peripheral ring where the oxide layer would otherwise be exposed.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 15, 2015
    Assignee: SOITEC
    Inventors: Didier Landru, Fabrice Gritti, Eric Guiot, Oleg Kononchuk, Christelle Veytizou
  • Publication number: 20140030877
    Abstract: A process for avoiding formation of a Si—SiO2—H2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of a Si—SiO2—H2 environment on the peripheral ring where the oxide layer would otherwise be exposed.
    Type: Application
    Filed: October 2, 2013
    Publication date: January 30, 2014
    Applicant: SOITEC
    Inventors: Didier LANDRU, Fabrice GRITTI, Eric GUIOT, Oleg KONONCHUK, Christelle VEYTIZOU
  • Patent number: 8343850
    Abstract: A process for fabricating a substrate that includes a buried oxide layer for the production of electronic components or the like. The process includes depositing an oxide layer or a nitride layer on either of a donor or receiver substrate, and bringing the donor and receiver substrates into contact; conducting at least a first heat treatment of the oxide or nitride layer before bonding the substrates, and conducting a second heat treatment of the fabricated substrate of the receiver substrate, the oxide layer and all or part of the donor substrate at a temperature equal to or higher than the temperature applied in the first heat treatment. Substrates that have an oxide or nitride layer deposited thereon wherein the oxide or nitride layer is degassed and has a refractive index smaller than the refractive index of an oxide or nitride layer of the same composition formed by thermal growth.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: January 1, 2013
    Assignee: Soitec
    Inventors: Eric Guiot, Fabrice Lallement
  • Patent number: 8324072
    Abstract: A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Soitec
    Inventors: Christelle Veytizou, Fabrice Gritti, Eric Guiot, Oleg Kononchuk, Didier Landru