Patents by Inventor Eric Guiot

Eric Guiot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090325362
    Abstract: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.
    Type: Application
    Filed: July 15, 2009
    Publication date: December 31, 2009
    Inventors: Nabil Chhaimi, Eric Guiot, Patrick Reynaud, Bruno Ghyselen, Cécile Aulnette, Bénédicte Osternaud, Takeshi Akatsu, Bruce Faure
  • Patent number: 7256103
    Abstract: The invention relates to a method for manufacturing a compound material wafer. The technique includes forming a weakened zone in a source substrate, attaching the source substrate to a handle substrate to form a source-handle assembly, and thermally annealing the source-handle assembly to further weaken the weakened zone. The method also includes holding the assembly at a holding temperature, and detaching the source substrate from the assembly at the weakened zone at the holding temperature. The holding temperature is greater than room temperature but does not promote further weakening of the weakened zone.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: August 14, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Thibaut Maurice, Phuong Nguyen, Eric Guiot
  • Patent number: 7217639
    Abstract: The invention relates to a method for manufacturing a material compound wafer by forming a predetermined splitting area in a source substrate; attaching the source substrate to a handle substrate to form an assembly; heating the assembly for weakening the predetermined splitting area; and determining a degree of weakening of the predetermined splitting area which evidences the physical strength of the predetermined splitting area during or after heating to detect anomalies that may lead to damage of the source substrate, handle or assembly. The degree of weakening is advantageously determined in-situ and may be determined continuously or periodically during the heating. The invention further relates to an apparatus for thermal annealing device used in the manufacturing process of a material compound wafer.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: May 15, 2007
    Assignee: S.O.I. Tec Silicon on Insulator Technologies S.A.
    Inventors: Thibaut Maurice, Eric Guiot
  • Publication number: 20070105246
    Abstract: The invention relates to a device for use in a method for manufacturing a material compound wafer by forming a predetermined splitting area in a source substrate; attaching the source substrate to a handle substrate to form an assembly; heating the assembly for weakening the predetermined splitting area; and determining a degree of weakening of the predetermined splitting area which evidences the physical strength of the predetermined splitting area during or after heating to detect anomalies that may lead to damage of the source substrate, handle or assembly. The device is includes an annealing device for thermally annealing the assembly; and a measuring device for determining the degree of weakening of the predetermined splitting area during or after thermal annealing to detect anomalies that may lead to damage of the source substrate, handle or assembly. The degree of weakening is advantageously determined in-situ and may be determined continuously or periodically during the heating.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Thibaut Maurice, Eric Guiot
  • Publication number: 20070087526
    Abstract: A method for forming a semiconductor structure comprising a thin layer of semiconductor material on a receiver wafer is disclosed. The method comprises removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.
    Type: Application
    Filed: March 21, 2006
    Publication date: April 19, 2007
    Inventors: Nabil Chhaimi, Eric Guiot, Patrick Reynaud
  • Publication number: 20050277269
    Abstract: The invention relates to a method for manufacturing a material compound wafer by forming a predetermined splitting area in a source substrate; attaching the source substrate to a handle substrate to form an assembly; heating the assembly for weakening the predetermined splitting area; and determining a degree of weakening of the predetermined splitting area which evidences the physical strength of the predetermined splitting area during or after heating to detect anomalies that may lead to damage of the source substrate, handle or assembly. The degree of weakening is advantageously determined in-situ and may be determined continuously or periodically during the heating. The invention further relates to an apparatus for thermal annealing device used in the manufacturing process of a material compound wafer.
    Type: Application
    Filed: December 3, 2004
    Publication date: December 15, 2005
    Inventors: Thibaut Maurice, Eric Guiot
  • Publication number: 20050277267
    Abstract: The invention relates to a method for manufacturing a compound material wafer. The technique includes forming a weakened zone in a source substrate, attaching the source substrate to a handle substrate to form a source-handle assembly, and thermally annealing the source-handle assembly to further weaken the weakened zone. The method also includes holding the assembly at a holding temperature, and detaching the source substrate from the assembly at the weakened zone at the holding temperature. The holding temperature is greater than room temperature but does not promote further weakening of the weakened zone.
    Type: Application
    Filed: November 9, 2004
    Publication date: December 15, 2005
    Inventors: Thibaut Maurice, Phuong Nguyen, Eric Guiot
  • Publication number: 20050130393
    Abstract: A method for improving the quality of a heterostructure that includes at least two layers of material that have different thermal expansion coefficients is described. The method includes applying a cap layer to the exposed surface of at least one of the layers. The cap layer is made of a material and has a thickness sufficient to reduce defects in at least one of the two layers during subsequent thermal treatment of the heterostructure. The present technique is a reliable and effective method for improving the quality of a heterostructure.
    Type: Application
    Filed: May 5, 2004
    Publication date: June 16, 2005
    Inventors: Beryl Blondeau, Ian Cayrefourcq, Eric Guiot, Thibaut Maurice, Hubert Moriceau