Abstract: A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

Abstract: To improve the scheduling and tasking of resources, the present disclosure describes an improved planning system and method for the allocation and management of resources. The planning system uses a branch and bound approach of tasking resources using a heuristic to expedite arrival at a deterministic solution. For each possible functional mode of the resources, an upper bound is determined. The upper bounds are employed in an objective function for the branch and bound process to determine the functional mode in which to place the resources and to determine movement paths for the resources, all in an environment where a hostile force may attempt to destroy the resources.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

Abstract: A hybrid probabilistic/deterministic planning system including a hybrid planning engine responsive to a null hybrid contingency plan including user defined probabilistic problem including goals, possible effect actions, and the initial state of one or more possible worlds configured to extract a deterministic planning problem therefrom. A deterministic planning engine responsive to the hybrid planning engine configured to generate one or more deterministic partial plans. The d hybrid planning engine converts the one or more deterministic partial plans into one or more hybrid partial plans and splices the one or more hybrid partial plans into selected null hybrid contingency plans to generate one or more hybrid contingency plans for each agent in each of the one or more possible worlds.

Abstract: To improve the scheduling and tasking of resources, the present disclosure describes an improved planning system and method for the allocation and management of resources. The planning system uses a branch and bound approach of tasking resources using a heuristic to expedite arrival at a deterministic solution. For each possible functional mode of the resources, an upper bound is determined. The upper bounds are employed in an objective function for the branch and bound process to determine the functional mode in which to place the resources and to determine movement paths for the resources, all in an environment where a hostile force may attempt to destroy the resources.

Abstract: A method of correcting and detecting errors in a sector of data stored in a DVD format is provided. The method includes: calculating an initial error detection value for data within the sector, performing an error correction operation on the data within the sector and determining an updated, intermediate error detection value responsive to the error correction operation, using a target error detection value and one of the initial error detection value and the intermediate error detection value to determine that the sector doesn't include errors, processing an outer code to provide a set of error patterns and error locations, and determining if any of the error locations are for data within the sector and not correcting data corresponding to the error locations within the sector.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

Abstract: A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate.

Abstract: This invention relates to a pendulum assembly within a laser levelling apparatus. In use, the assembly is rotatably mounted with the levelling device to hang under the effect of gravity such that opposed light emitting devices produce light on a horizontal plane. The assembly includes a main body rotatably mountable in the levelling apparatus and at least two light emitting devices mounted in or on light emitting mounting portions. At least one of the light emitting mounting positions is rotatably mounted to the main body and adjustable in its orientation with respect to the main body by an threaded adjustment means. Once one light emitting device is mounted, the adjustable one can be brought into a substantially co-linear position by movement of the threaded adjustment means. A further embodiment includes a further light emitter acting on a reflective surface to provide a substantially vertical light.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.

Abstract: Methods and apparatus to perform process placement for distributed applications are disclosed. An example method comprises determining a mapping between a communication graph representative of communications of a distributed application and a topology graph representative of communication costs associated with a computing network, and executing the distributed application with the processes of the distributed application assigned to the processing entities of the computing network based upon the mapping.

Abstract: Methods and apparatus to provide techniques for planners that records constraints over a set of numeric state variables for each fact and characterizes the set of states in which that fact is true to provide more information to reason about mutual exclusions among sets of states offering a tighter bound on the metric cost of a plan than existing planners currently attain. This more accurate estimate can avoid irrelevant states and decrease search times.

Abstract: Method and apparatus for an adversarial planner to create a first plan for a first agent and a second plan for a second agent, wherein the first and second plans are independent, identify conflicts between the first and second plans, and address the identified conflicts by planning a contingency branch for one of the agents that resolves the conflict in the agent's favor, and splicing that new branch into the agent's plan.

Abstract: A method of correcting and detecting errors in a sector of data stored in a DVD format is provided. The method includes: calculating an initial error detection value for data within the sector, performing an error correction operation on the data within the sector and determining an updated, intermediate error detection value responsive to the error correction operation, using a target error detection value and one of the initial error detection value and the intermediate error detection value to determine that the sector doesn't include errors, processing an outer code to provide a set of error patterns and error locations, and determining if any of the error locations are for data within the sector and not correcting data corresponding to the error locations within the sector.