Patents by Inventor Eric J. Hoffman

Eric J. Hoffman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10660544
    Abstract: A patient support apparatus includes detectors and a controller operable to automatically update a tare weight for use in determining a true patient weight. The detectors are configured to produce signals indicating a presence or absence of a corresponding removable component. The controller is configured to determine weights of each and every removable component on the patient support apparatus and store each weight in a memory. The controller is further configured to receive the signals produced by the detectors and detect any addition or removal of removable components of the patient support apparatus, update the tare weight, and determine a weight of a patient being supported on the patient support apparatus.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 26, 2020
    Assignee: Hill-Rom Services, Inc.
    Inventors: Brian J. Hoffman, Mike J. Viltro, Chris L. Hildenbrand, James L. Walke, Aziz A. Bhai, Eric R. Meyer, David C. Newkirk, Frank Sauser, Nicole Johannigman, Brandon P. Fisk
  • Publication number: 20190335964
    Abstract: A blower includes a main body which includes a housing and a fan disposed in the housing. The housing further defines an air discharge opening. The blower further includes an extension tube connected to the air discharge opening, the extension tube extending between a first end connected to the air discharge opening and a second end. The blower further includes a variable nozzle, the variable nozzle including a plurality of adjustable air control surfaces. The blower further includes a nozzle adjustment tube connected to the second end of the extension tube and at least partially surrounding the variable nozzle.
    Type: Application
    Filed: April 9, 2019
    Publication date: November 7, 2019
    Inventors: Ronald J. Hoffman, Christopher A. Holman, Eric Nolin
  • Patent number: 10306830
    Abstract: A winding mechanism, a string trimmer head, and a method of winding line. The head may include a body, and a spool supported by the body, a line being supportable by the spool. The winding mechanism may include a crank engageable to rotate the spool to wind the line onto the spool. The trimmer head may include a bump knob engageable with the spool, and the crank may include a crank body engageable with the bump knob to rotate the spool. The crank may further include an arm connected to the crank body and a handle connected to the arm and engageable by a user to pivot the crank.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 4, 2019
    Assignee: TTI (MACAO COMMERCIAL OFFSHORE) LIMITED
    Inventors: Eric Nolin, Ronald J. Hoffman, Christopher A. Holman
  • Patent number: 8422249
    Abstract: A microinverter is disclosed for use in a solar power installation. The microinverter incorporates a voltage-to-current control loop that initially converts output current produced by a photovoltaic panel into a pulse width modulated output synchronized and phase-locked to the utility grid voltage. The duty cycle of that modulated output is specified by output power internally requested from the microinverter. This modulated output is converted into a full-wave rectified unipolar waveform that is converted, through a Commutator, into a bipolar AC output that is also phase-locked and synchronized to the grid voltage. The commutator uses an H-bridge composed of four FETs, with each of two diagonally-oriented pairs of these FETs being advantageously switched on substantially at zero-crossing points in the grid voltage.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: April 16, 2013
    Assignee: Direct Grid Technologies, LLC
    Inventors: Frank G. Cooper, Eric J. Hoffman, Richard MacArthur
  • Publication number: 20130051092
    Abstract: A microinverter is disclosed for use in a solar power installation. The microinverter incorporates a voltage-to-current control loop that initially converts output current produced by a photovoltaic panel into a pulse width modulated output synchronized and phase-locked to the utility grid voltage. The duty cycle of that modulated output is specified by output power internally requested from the microinverter. This modulated output is converted into a full-wave rectified unipolar waveform that is converted, through a Commutator, into a bipolar AC output that is also phase-locked and synchronized to the grid voltage. The commutator uses an H-bridge composed of four FETs, with each of two diagonally-oriented pairs of these FETs being advantageously switched on substantially at zero-crossing points in the grid voltage.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Direct Grid Technologies LLC
    Inventors: Frank G. Cooper, Eric J. Hoffman, Richard MacArthur
  • Patent number: 8358506
    Abstract: A mechanical arrangement for use in implementing a galvanically-isolated, low-profile micro-inverter primarily, though not exclusively, intended for use with solar panels. The micro-inverter contains a circuitry assembly having a planar transformer formed of two abutting E-shaped core halves, and a chopper device assembly with all chopper devices mounted to a common thermally-conductive plate. To provide passive cooling, heat conduction paths are established, via separate compressive thermally-conductive pads, from a top surface of a top core half of the transformer and from a bottom surface of the conductive plate to large-area portions of opposing internal surfaces of top and base portions, respectively, of an enclosure.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 22, 2013
    Assignee: Direct Grid Technologies, LLC
    Inventors: Frank G. Cooper, Eric J. Hoffman
  • Publication number: 20120050999
    Abstract: A mechanical arrangement for use in implementing a galvanically-isolated, low-profile micro-inverter primarily, though not exclusively, intended for use with solar panels. The micro-inverter contains a circuitry assembly having a planar transformer formed of two abutting E-shaped core halves, and a chopper device assembly with all chopper devices mounted to a common thermally-conductive plate. To provide passive cooling, heat conduction paths are established, via separate compressive thermally-conductive pads, from a top surface of a top core half of the transformer and from a bottom surface of the conductive plate to large-area portions of opposing internal surfaces of top and base portions, respectively, of an enclosure.
    Type: Application
    Filed: August 27, 2010
    Publication date: March 1, 2012
    Applicant: Direct Grid Technologies LLC
    Inventors: Frank G. Cooper, Eric J. Hoffman
  • Patent number: 7010706
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: March 7, 2006
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Neil F. Deutscher, Eric J. Hoffman
  • Patent number: 6944784
    Abstract: Briefly, in accordance with one embodiment of the invention, a flip-flop operates as a master-slave flip flop in a test mode and operates as a pulsed latch in normal operation. Two clock signals having non-overlapping transitions are used to provide and control the flow of input data.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 13, 2005
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Eric J. Hoffman, Susan M. Graham, Dale J. Brown
  • Patent number: 6522357
    Abstract: In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: February 18, 2003
    Assignee: Intel Corporation
    Inventors: Mark A. Beiley, Eric J. Hoffman, Lawrence T. Clark
  • Publication number: 20030005347
    Abstract: Briefly, in accordance with one embodiment of the invention, a flip-flop operates as a master-slave flip flop in a test mode and operates as a pulsed latch in normal operation. Two clock signals having non-overlapping transitions are used to provide and control the flow of input data.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Lawrence T. Clark, Eric J. Hoffman, Susan M. Graham, Dale J. Brown
  • Publication number: 20020152410
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.
    Type: Application
    Filed: April 13, 2001
    Publication date: October 17, 2002
    Inventors: Lawrence T. Clark, Neil F. Deutscher, Eric J. Hoffman
  • Patent number: 6456110
    Abstract: A voltage level shifter for changing digital bit levels between devices having different voltage levels. In addition to changing the voltage levels in the normal mode, the device includes additional transistors which are activated when the system is in a drowsy mode so as to cut DC current drain and to latch outputs to ignore extraneous inputs.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: September 24, 2002
    Assignee: Intel Corporation
    Inventors: Pradeep Elamanchili, Eric J. Hoffman
  • Patent number: 6433822
    Abstract: An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: August 13, 2002
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Mark A. Beiley, Eric J. Hoffman
  • Publication number: 20020085106
    Abstract: In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.
    Type: Application
    Filed: September 30, 1997
    Publication date: July 4, 2002
    Inventors: MARK A. BEILEY, ERIC J. HOFFMAN, LAWRENCE T. CLARK
  • Publication number: 20020084802
    Abstract: A voltage level shifter for changing digital bit levels between devices having different voltage levels. In addition to changing the voltage levels in the normal mode, the device includes additional transistors which are activated when the system is in a drowsy mode so as to cut DC current drain and to latch outputs to ignore extraneous inputs.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Pradeep Elamanchili, Eric J. Hoffman
  • Patent number: 6388315
    Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: May 14, 2002
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do
  • Patent number: 6368933
    Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: April 9, 2002
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do
  • Patent number: RE42776
    Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: October 4, 2011
    Assignee: Marvell International Ltd.
    Inventors: Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do
  • Patent number: RE43326
    Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do