Abstract: A microinverter is disclosed for use in a solar power installation. The microinverter incorporates a voltage-to-current control loop that initially converts output current produced by a photovoltaic panel into a pulse width modulated output synchronized and phase-locked to the utility grid voltage. The duty cycle of that modulated output is specified by output power internally requested from the microinverter. This modulated output is converted into a full-wave rectified unipolar waveform that is converted, through a Commutator, into a bipolar AC output that is also phase-locked and synchronized to the grid voltage. The commutator uses an H-bridge composed of four FETs, with each of two diagonally-oriented pairs of these FETs being advantageously switched on substantially at zero-crossing points in the grid voltage.

Abstract: A microinverter is disclosed for use in a solar power installation. The microinverter incorporates a voltage-to-current control loop that initially converts output current produced by a photovoltaic panel into a pulse width modulated output synchronized and phase-locked to the utility grid voltage. The duty cycle of that modulated output is specified by output power internally requested from the microinverter. This modulated output is converted into a full-wave rectified unipolar waveform that is converted, through a Commutator, into a bipolar AC output that is also phase-locked and synchronized to the grid voltage. The commutator uses an H-bridge composed of four FETs, with each of two diagonally-oriented pairs of these FETs being advantageously switched on substantially at zero-crossing points in the grid voltage.

Abstract: A mechanical arrangement for use in implementing a galvanically-isolated, low-profile micro-inverter primarily, though not exclusively, intended for use with solar panels. The micro-inverter contains a circuitry assembly having a planar transformer formed of two abutting E-shaped core halves, and a chopper device assembly with all chopper devices mounted to a common thermally-conductive plate. To provide passive cooling, heat conduction paths are established, via separate compressive thermally-conductive pads, from a top surface of a top core half of the transformer and from a bottom surface of the conductive plate to large-area portions of opposing internal surfaces of top and base portions, respectively, of an enclosure.

Abstract: A mechanical arrangement for use in implementing a galvanically-isolated, low-profile micro-inverter primarily, though not exclusively, intended for use with solar panels. The micro-inverter contains a circuitry assembly having a planar transformer formed of two abutting E-shaped core halves, and a chopper device assembly with all chopper devices mounted to a common thermally-conductive plate. To provide passive cooling, heat conduction paths are established, via separate compressive thermally-conductive pads, from a top surface of a top core half of the transformer and from a bottom surface of the conductive plate to large-area portions of opposing internal surfaces of top and base portions, respectively, of an enclosure.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.

Abstract: Briefly, in accordance with one embodiment of the invention, a flip-flop operates as a master-slave flip flop in a test mode and operates as a pulsed latch in normal operation. Two clock signals having non-overlapping transitions are used to provide and control the flow of input data.

Abstract: In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

Abstract: Briefly, in accordance with one embodiment of the invention, a flip-flop operates as a master-slave flip flop in a test mode and operates as a pulsed latch in normal operation. Two clock signals having non-overlapping transitions are used to provide and control the flow of input data.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.

Abstract: A voltage level shifter for changing digital bit levels between devices having different voltage levels. In addition to changing the voltage levels in the normal mode, the device includes additional transistors which are activated when the system is in a drowsy mode so as to cut DC current drain and to latch outputs to ignore extraneous inputs.

Abstract: An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.

Abstract: A voltage level shifter for changing digital bit levels between devices having different voltage levels. In addition to changing the voltage levels in the normal mode, the device includes additional transistors which are activated when the system is in a drowsy mode so as to cut DC current drain and to latch outputs to ignore extraneous inputs.

Abstract: In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Abstract: An apparatus comprising a charge pump configured to receive an input signal and to output incrementally a fixed amount of voltage for every selected edge of the input signal, an analog buffer coupled to said charge pump, the analog buffer feeding back a second voltage to said charge pump, the output of the charge pump linearly increases as a function of the fixed amount of voltage. A low power ramp generator that is created thereby may be used in analog to digital converters which are employed in devices such as imaging systems.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.