Patents by Inventor Eric J. Li
Eric J. Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190355666Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.Type: ApplicationFiled: July 12, 2019Publication date: November 21, 2019Applicant: Intel CorporationInventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
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Patent number: 10418329Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.Type: GrantFiled: December 11, 2015Date of Patent: September 17, 2019Assignee: Intel CorporationInventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
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Publication number: 20190259713Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.Type: ApplicationFiled: February 20, 2019Publication date: August 22, 2019Applicant: INTEL CORPORATIONInventors: ERIC J. LI, GUOTAO WANG, HUIYANG FEI, SAIRAM AGRAHARAM, OMKAR G. KARHADE, NITIN A. DESHPANDE
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Patent number: 10373888Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.Type: GrantFiled: December 30, 2016Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Eric J. Li, Vipul V. Mehta, Digvijay A. Raorane
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Patent number: 10256198Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.Type: GrantFiled: March 23, 2017Date of Patent: April 9, 2019Assignee: INTEL CORPORATIONInventors: Eric J. Li, Guotao Wang, Huiyang Fei, Sairam Agraharam, Omkar G. Karhade, Nitin A. Deshpande
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Patent number: 10256205Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.Type: GrantFiled: November 14, 2017Date of Patent: April 9, 2019Assignee: Intel CorporationInventors: Eric J. Li, Jimin Yao, Shawna M. Liff
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Publication number: 20190096838Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.Type: ApplicationFiled: November 21, 2018Publication date: March 28, 2019Applicant: Intel CorporationInventors: Eric J. Li, Jimin Yao, Shawna M. Liff
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Patent number: 10224223Abstract: Vacuum processing, such as a backside metallization (BSM) deposition, is performed on a taped wafer after a gas escape path is formed between a base film of the tape and the wafer frontside surface following backgrind. Venting provided by the gas escape path reduces formation of bubbles under the tape. The gas escape path may be provided, for example, by a selective pre-curing of tape adhesive, to breach an edge seal and place the wafer frontside surface internal to the edge seal in fluid communication with an environment external to the edge seal. With the thinned wafer supported by the pre-cured tape, BSM is then deposited while the wafer and tape are cooled, for example, via a cooled electrostatic chuck.Type: GrantFiled: June 20, 2016Date of Patent: March 5, 2019Assignee: Intel CorporationInventor: Eric J. Li
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Patent number: 10163810Abstract: Embodiments are generally directed to electromagnetic interference shielding for system-in-package technology. An embodiment of a system-in-package includes a substrate; chips and components attached to the substrate; dielectric molding over the chips and components; and an electromagnetic interference (EMI) shield. The EMI shield formed from a conductive paste, and the EMI shield provides a combined internal EMI shield between chips and components of the system in package and external EMI shield for the system-in-package.Type: GrantFiled: December 26, 2015Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Eric J. Li, Yoshihiro Tomita, Nachiket R. Raravikar, Robert L. Sankman
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Publication number: 20180358296Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.Type: ApplicationFiled: December 22, 2015Publication date: December 13, 2018Inventors: Eric J. LI, Nitin DESHPANDE, Shawna M. LIFF, Omkar KARHADE, Amram EITAN, Timothy A. GOSSELIN
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Publication number: 20180337129Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.Type: ApplicationFiled: December 11, 2015Publication date: November 22, 2018Applicant: Intel CorporationInventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
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Publication number: 20180337135Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.Type: ApplicationFiled: December 22, 2015Publication date: November 22, 2018Inventors: Tomita YOSHIHIRO, Eric J. LI, Shawna M. LIFF, Javier A. FALCON, Joshua D. HEPPNER
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Publication number: 20180331051Abstract: Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first die. In one example, the second die is formed with compound semiconductor materials. The microelectronic device includes a substrate that is coupled to the first die with a plurality of electrical connections. The substrate including an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.Type: ApplicationFiled: December 22, 2015Publication date: November 15, 2018Inventors: Georgios C. DOGIAMIS, Telesphor KAMGAING, Eric J. LI, Sr., Javier A. FALCON, Yoshihiro TOMITA, Vijay K. NAIR, Shawna M. LIFF
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Patent number: 10121722Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.Type: GrantFiled: September 30, 2017Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Chandra M. Jha, Eric J. Li, Zhaozhi Li, Robert M. Nickerson
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Publication number: 20180277492Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.Type: ApplicationFiled: March 23, 2017Publication date: September 27, 2018Applicant: INTEL CORPORATIONInventors: ERIC J. LI, GUOTAO WANG, HUIYANG FEI, SAIRAM AGRAHARAM, OMKAR G. KARHADE, NITIN A. DESHPANDE
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Publication number: 20180226358Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.Type: ApplicationFiled: April 4, 2018Publication date: August 9, 2018Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
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Publication number: 20180190560Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Applicant: Intel CorporationInventors: Eric J. Li, Vipul V. Mehta, Digvijay A. Raorane
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Patent number: 9953929Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.Type: GrantFiled: March 18, 2016Date of Patent: April 24, 2018Assignee: Intel CorporationInventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
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Patent number: 9922751Abstract: A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.Type: GrantFiled: April 1, 2016Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Eric J. Li, Kemal Aygun
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Publication number: 20180068969Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.Type: ApplicationFiled: November 14, 2017Publication date: March 8, 2018Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff