Abstract: In one embodiment, a power amplifier may include a bridge configuration having a first pair of gain transistors to receive a first portion of a differential signal and to amplify the first portion of the differential signal to an amplified first differential signal portion and a second pair of gain transistors to receive a second portion of the differential signal and to amplify the second portion of the differential signal to an amplified second differential signal portion. This second pair of gain transistors can be configured to be enabled in a first power mode and to be disabled in a second power mode.

Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

Abstract: In one embodiment, a power amplifier may include an output stage with multiple transformers and corresponding matching capacitances. The capacitances may include a first matching capacitance coupled in parallel with a secondary coil of a first transformer and a second matching capacitance coupled in parallel with a secondary coil of a second transformer, where the secondary coils are coupled in series in an output stack configuration. By accounting for parasitics present in the power amplifier, the first matching capacitance can be designed to have a greater capacitance than the second matching capacitor, even where the first and second transformers are configured to output substantially equal power levels.

Abstract: In one embodiment, the present invention includes a transformer formed on a semiconductor die. Such transformer may have multiple coils, including first and second coils. Each coil may have segments that in turn are formed on a corresponding metal layer of the semiconductor die. The segments of a given coil are coupled to each other, and the first and second coils can be interdigitated with each other.

Abstract: In one embodiment, a power amplifier may include an output stage with multiple transformers and corresponding matching capacitances. The capacitances may include a first matching capacitance coupled in parallel with a secondary coil of a first transformer and a second matching capacitance coupled in parallel with a secondary coil of a second transformer, where the secondary coils are coupled in series in an output stack configuration. By accounting for parasitics present in the power amplifier, the first matching capacitance can be designed to have a greater capacitance than the second matching capacitor, even where the first and second transformers are configured to output substantially equal power levels.

Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

Abstract: GBit/s transceiver with built-in self test features. A method is disclosed for testing the operation of a transceiver having a digital processing section and an analog section, each having a transmit portion and a receive portion, the analog portions adaptable to interface with an analog network. The transceiver is first configured to operate in a test mode. In the test mode, the transmit portion of the digital processing section is activated to generate data to be transmitted by the transmit portion of the analog section. The receive portion of the analog section and the receive portion of the digital processing section are operated to receive data. Thereafter, the parametrics of select portions of the receive portion of the digital processing section are examined during the receipt of data by the receive portion of the analog section and processing thereof by the receive portion of the digital processing section.

Abstract: A multi-path unity gain buffer circuit and method are implemented in a slew amplifier. The multi-path unity buffer has a high frequency signal path and a low frequency signal path. The high frequency signal path has a differential amplifier powered for providing a high frequency, low accuracy buffering operation. The low frequency signal path is coupled to the high frequency signal path. The low frequency signal path has an operational amplifier powered to provide a low frequency, high bandwidth buffering operation. An output of the operational amplifier is fed back to an input of the operational amplifier through a current varying element that varies current levels of the input of the operational amplifier to remove a level shift of an output signal of the differential amplifier.

Abstract: An output driver (121) for a 10BaseT/100BaseTX transceiver provides a drive capability for either a 10BaseT output or a 100BaseTX output. The driver includes a voltage-to-current converter for converting the voltage to a current level which is then selectably switched to the input of two constant output impedance buffers (327) and (328). For the 100BaseTX mode, a constant current is provided to the buffers and then the current switched in a multi-level mode in accordance with an MLT-3 encoding scheme with a current switch (311). The buffers (327) and (328) are trimmed as a function of temperature by varying the current generated by the voltage-to-current converter (303). This trimming is facilitated by generating an internal current with the voltage-to-current converter (303) and then summing therewith a zero temperature coefficient current referenced to an external resistor.