Patents by Inventor Eric Kline
Eric Kline has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160030562Abstract: Herein are provided methods for reducing or eliminating cancer in a patient in need of cancer treatment, by providing cholesterol deprivation therapy (CDT) in conjunction with antibodies directed against cholesterol-deprived tumor cells. Further provided are methods of enhancing the efficacy of other cancer treatments, by administering CDT and antibodies directed against cholesterol-deprived tumor cells, in combination with additional anti-cancer therapies.Type: ApplicationFiled: October 15, 2015Publication date: February 4, 2016Inventor: Eric Kline
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Patent number: 8636052Abstract: An integrated circuit dual-fluid heat exchanger has a housing containing first and second immiscible fluids. A heat-introducing base element contacts the first fluid. A heat-receiving surface on the base element is configured for interfacial contact with a heat-radiating surface of an integrated circuit device. A heat-removing condenser element contacts the second fluid, or is separated therefrom by a gap. The first and second fluids are selected to controllably remove heat from the integrated circuit device by forming heated mass units of the first fluid that migrate through the second fluid and come into contact with the condenser element, where they are cooled and allowed to return to the base element. A heat-expulsion portion on the condenser element is configured to dissipate heat removed by the condenser element to an exterior environment outside the heat exchanger.Type: GrantFiled: September 8, 2009Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Eric Kline, Paul N. Krystek, Paul R. Michels, Susan J. Swenson, Stephen M. Zins
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Publication number: 20130131432Abstract: Disclosed is a method to use tuned resonant frequency ultrasonic energy for treatment of cancer that selectively destroys neoplastic cells while leaving surrounding healthy tissue minimally affected.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Eric Kline
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Publication number: 20130131557Abstract: Disclosed is a method to use tuned resonant frequency ultrasonic energy for treatment of cancer that selectively destroys neoplastic cells while leaving surrounding healthy tissue minimally affected.Type: ApplicationFiled: November 21, 2011Publication date: May 23, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Eric Kline
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Publication number: 20130064811Abstract: Herein are provided methods for reducing or eliminating cancer in a patient in need of cancer treatment, by providing cholesterol deprivation therapy (CDT) in conjunction with antibodies directed against cholesterol-deprived tumor cells. Further provided are methods of enhancing the efficacy of other cancer treatments, by administering CDT and antibodies directed against cholesterol-deprived tumor cells, in combination with additional anti-cancer therapies.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Eric Kline
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Patent number: 8278812Abstract: A grid component for use with a vacuum electron device (VED), such as an inductive output tube (IOT), includes a skirt that adds structural support and aids in alignment. The grid component has a dome in which a grid pattern is formed and includes an annular, concentric flange surrounding the dome. The skirt is formed concentrically around the flange. Alignment orifices may be provided in the flange for passage of alignment pins in the assembled product. The grid, flange, and skirt are a unitary component and are formed by a chemical vapor deposition (CVD) or similar process, in which a mandrel is used to provide a deposition surface. The mandrel is placed in a furnace, and a high-temperature CVD process is used to break down a hydrocarbon gas to thereby deposit a pyrolytic graphite coating onto the mandrel. The mandrel may include a skirt template to provide the characteristic skirt.Type: GrantFiled: January 7, 2008Date of Patent: October 2, 2012Assignee: Communications and Power Industries, Inc.Inventors: Edward Lawrence Eisen, James Eric Kline
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Publication number: 20110056655Abstract: An integrated circuit dual-fluid heat exchanger has a housing containing first and second immiscible fluids. A heat-introducing base element contacts the first fluid. A heat-receiving surface on the base element is configured for interfacial contact with a heat-radiating surface of an integrated circuit device. A heat-removing condenser element contacts the second fluid, or is separated therefrom by a gap. The first and second fluids are selected to controllably remove heat from the integrated circuit device by forming heated mass units of the first fluid that migrate through the second fluid and come into contact with the condenser element, where they are cooled and allowed to return to the base element. A heat-expulsion portion on the condenser element is configured to dissipate heat removed by the condenser element to an exterior environment outside the heat exchanger.Type: ApplicationFiled: September 8, 2009Publication date: March 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Kline, Paul N. Krystek, Paul R. Michels, Susan J. Swenson, Stephen M. Zins
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Patent number: 7737912Abstract: A portable electronic display device includes an electronic display surface having at least one display panel that displays a graphical and/or textual message, memory that stores a plurality of the messages, and one or more switches on the device that allow user selection of one of the messages. The device further includes a controller that disables the one or more switches if none of the switches are selected after a predetermined period of time after power is turned on to the display device, or if none of the switches are selected after a predetermined period of time subsequent to the last switch selection occurrence. In this manner, a person is prevented from subsequently changing the message via the one or more switches.Type: GrantFiled: February 9, 2005Date of Patent: June 15, 2010Assignee: Intuitive Control Systems, LLCInventors: John T. Graef, Eric Kline, Philip R. Hall
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Patent number: 7704802Abstract: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.Type: GrantFiled: October 12, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Harsaran S. Bhatia, Eric Kline
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Publication number: 20100090601Abstract: A grid component for use with a vacuum electron device (VED), such as an inductive output tube (IOT), includes a skirt that adds structural support and aids in alignment. The grid component has a dome in which a grid pattern is formed and includes an annular, concentric flange surrounding the dome. The skirt is formed concentrically around the flange. Alignment orifices may be provided in the flange for passage of alignment pins in the assembled product. The grid, flange, and skirt are a unitary component and are formed by a chemical vapor deposition (CVD) or similar process, in which a mandrel is used to provide a deposition surface. The mandrel is placed in a furnace, and a high-temperature CVD process is used to break down a hydrocarbon gas to thereby deposit a pyrolytic graphite coating onto the mandrel. The mandrel may include a skirt template to provide the characteristic skirt.Type: ApplicationFiled: January 7, 2008Publication date: April 15, 2010Applicant: Communications and power Industries, Inc.Inventors: Edward Lawrence Eisen, James Eric Kline
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Patent number: 7420248Abstract: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.Type: GrantFiled: August 25, 2005Date of Patent: September 2, 2008Assignee: International Business Machines CorporationInventors: Harsaran S. Bhatia, Eric Kline
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Publication number: 20080032460Abstract: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.Type: ApplicationFiled: October 12, 2007Publication date: February 7, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harsaran Bhatia, Eric Kline
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Patent number: 7325213Abstract: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.Type: GrantFiled: June 17, 2005Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Harsaran S. Bhatia, Marie S. Cole, Michael S. Cranmer, Jason Lee Frankel, Eric Kline, Kenneth A. Papae, Paul R. Walling
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Publication number: 20070045733Abstract: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.Type: ApplicationFiled: August 25, 2005Publication date: March 1, 2007Inventors: Harsaran Bhatia, Eric Kline
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Publication number: 20060280129Abstract: The present invention provides a method, system, and program product for the deployment and use of an intelligent sensor network. More particularly, the method, system, and program product of the present invention enable the deployment and use of fused sensors in an arbitrary area or volume. In a first aspect, the invention provides a method for employing a multi-sensor network, the method comprising the steps of employing a first sensor, employing a plurality of additional sensors, a position of each additional sensor within the network being relative in at least two dimensions to only one of the first sensor and an adjacent sensor nearer the first sensor, and employing a routing algorithm for determining a routing path for data in the network.Type: ApplicationFiled: June 14, 2005Publication date: December 14, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Kline, Harsaran Bhatia
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Publication number: 20060124340Abstract: Methods and an active device thread system are disclosed for electrically connecting an active device thread to an output. In one embodiment, an active device thread includes a substantially conical end that has elements of the thread exposed for coupling to a mating portion of an output. In an alternative embodiment, an active device thread includes a tapered cut that has elements of the thread exposed for coupling to a mating portion of an output. The invention also includes an active device thread system including an electrical connection including one of a substantially conical end that exposes at least two elements of the active device thread and a tapered cut that exposes at least two elements of the active device thread, and a mating portion on an output.Type: ApplicationFiled: December 9, 2004Publication date: June 15, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Eric Kline
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Publication number: 20050278674Abstract: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.Type: ApplicationFiled: June 17, 2005Publication date: December 15, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harsaran Bhatia, Marie Cole, Michael Cranmer, Jason Frankel, Eric Kline, Kenneth Papae, Paul Walling
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Publication number: 20050210722Abstract: A foldable electronic display, also known as a variable or changeable message sign, displays important or emergency messages for the control of roadway and highway traffic. The self-contained foldable electronic display is lightweight and portable and can be handled and setup easily and quickly by one person, on a multiplicity of structures. The display may be stowed in the luggage compartment of highway maintenance and emergency response vehicles in a folded orientation when not in use. During use, the display displays a stored or newly created message. A software lockout feature prevents the message from being changed using on-board controls by unauthorized personnel, eliminating the need for mechanical security measures. An optional mounting bracket apparatus assures that the foldable electronic display is held in an open orientation. The mounting bracket apparatus is installed in a manner that is tamperproof and does not allow unauthorized access to mounting hardware.Type: ApplicationFiled: February 9, 2005Publication date: September 29, 2005Inventors: John Graef, Eric Kline, Philip Hall
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Publication number: 20050202725Abstract: An apparatus for providing a controlled impedance directly to predetermined contact elements within a socket, thereby reducing the “distorting” nature of the electrical interconnection system. In an illustrative embodiment of the present invention, predetermined contacts of a socket may have a resistance, inductance, capacitance, or a combination thereof incorporated therein. In another illustrative embodiment, at least one active element(s) may also be incorporated into predefined contacts. In this manner, predefined contacts may “process” the corresponding signal in a predetermined manner, defined by the circuitry incorporated on the contact itself. Illustrative functions that may be performed include, but are not limited to, amplifying, analog-to-digital converting, digital-to-analog converting, predefined logic functions, or any other function that may be performed via a combination of active and/or passive elements including a microprocessor function.Type: ApplicationFiled: February 28, 2005Publication date: September 15, 2005Inventors: David Johnson, Eric Kline
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Patent number: 5903164Abstract: Apparatus for use in testing a semiconductor device located on a wafer. The apparatus includes a wafer body. A device contact region is located on the wafer body. Further, an active component region is coupled to the device contact region. A mechanism is provided for coupling the active component region to a remote testing device. The active component region may include test signal conditioning circuits and device testing circuits. The active component region may be formed integral the wafer body by silicon wafer processing techniques, such as silicon doping.Type: GrantFiled: November 12, 1996Date of Patent: May 11, 1999Assignee: JohnsTech International CorporationInventor: Eric Kline