Abstract: Aspects include receiving, at an operating system (OS) executing on a server, a notification that an error was detected during execution of a synchronous I/O operation issued by the OS to a persistent storage control unit (SCU). The notification is received from firmware executing on the server and it includes a command response block that includes error condition information about the error. The method can also include selecting, by the OS, a recovery operation for the synchronous I/O operation. The selecting is based on the error condition information about the error in the command response block. The selected recovery option is performed by the OS.

Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

Abstract: Aspects include receiving, at an operating system (OS) executing on a server, a notification that an error was detected during execution of a synchronous I/O operation issued by the OS to a persistent storage control unit (SCU). The notification is received from firmware executing on the server and it includes a command response block that includes error condition information about the error. The method can also include selecting, by the OS, a recovery operation for the synchronous I/O operation. The selecting is based on the error condition information about the error in the command response block. The selected recovery option is performed by the OS.

Abstract: Aspects include receiving, at an operating system (OS) executing on a server, a notification that an error was detected during execution of a synchronous I/O operation issued by the OS to a persistent storage control unit (SCU). The notification is received from firmware executing on the server and it includes a command response block that includes error condition information about the error. The method can also include selecting, by the OS, a recovery operation for the synchronous I/O operation. The selecting is based on the error condition information about the error in the command response block. The selected recovery option is performed by the OS.

Abstract: Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.

Abstract: Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.

Abstract: A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message.

Abstract: A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.

Abstract: Embodiments include a method and computer program product for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router routes requests received over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.

Abstract: Embodiments of the present disclosure use non-blocking writes (NBWs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using NBWs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may indicate that a TLP includes an NBW. Based on the indication, the root complex may send the NBWs on a dedicated NBW channel such that the NBW is not blocked by normal memory writes.

Abstract: Embodiments include a system for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router receives requests over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.

Abstract: Embodiments relate to an implementation of a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge. An aspect includes an access of the device table in the system memory by a switch coupled to the host bridge, management of a device table entry (DTE) cache in the host bridge for coherency for DTE configuration changes and maintenance of a usage count and an in-use count in the host bridge for each cached DTE.

Abstract: DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.

Abstract: A data processing system includes a processor core, a system memory including a first data structure including entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers and a second data structure, and an input/output (I/O) subsystem including an I/O bridge and a plurality of PEs each including one or more requesters each having a respective requester ID. The I/O host bridge, responsive to receiving an I/O message including a requester ID, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index, where the second entry indicating one or more of the plurality of PEs affected by the message. The I/O host bridge services the I/O message with reference to each of the plurality of PEs indicated by the second entry.

Abstract: DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.

Abstract: Embodiments of the invention relate to non-standard input/output (I/O) adapters in a standardized I/O architecture. An aspect of the invention includes implementing non-standard I/O adapters in a standardized I/O architecture. A request is received at an I/O adapter from a requester to perform an operation on one of the I/O adapters. It is determined that the request is in a format other than a format supported by an I/O bus and that the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus, and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus. The completion response is transmitted to the requester.

Abstract: A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester.

Abstract: Embodiments relate to an implementation of system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge. Cache hint controls are defined in a packet header for a memory request. The cache hint controls are configured to issue an instruction to retain a copy of a memory element in a cache structure.

Abstract: An extension of a page table is provided. An aspect includes receiving, by a host bridge, a request. An aspect includes determining, by the host bridge, that access to a memory address space referenced by the request is authorized based on a requester identifier associated with the request. An aspect includes, based on determining that access to the memory address space is authorized, accessing, by the host bridge, a page included in the memory address space based on a combination of: a start of the page table and a single extended index.

Abstract: Embodiments are directed to a method and a computer program product for extending a page table. In an embodiment, the method comprises receiving, by a host bridge, a request. The method further comprises determining, by the host bridge, that access to a memory address space referenced by the request is authorized based on a requester identifier associated with the request. Based on determining that access to the memory address space is authorized, the method comprises accessing, by the host bridge, a page included in the memory address space based on a combination of: a start of the page table and a single extended index.