Patents by Inventor Eric N. Lais
Eric N. Lais has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150261679Abstract: Embodiments relate to an implementation of system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge. Cache hint controls are defined in a packet header for a memory request. The cache hint controls are configured to issue an instruction to retain a copy of a memory element in a cache structure.Type: ApplicationFiled: September 30, 2014Publication date: September 17, 2015Inventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
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Publication number: 20150261707Abstract: Embodiments include a method and computer program product for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router routes requests received over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.Type: ApplicationFiled: September 30, 2014Publication date: September 17, 2015Inventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
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Publication number: 20150261705Abstract: Embodiments include a system for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router receives requests over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: International Business Machines CorporationInventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
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Publication number: 20150261701Abstract: Embodiments relate to an implementation of a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge. An aspect includes an access of the device table in the system memory by a switch coupled to the host bridge, management of a device table entry (DTE) cache in the host bridge for coherency for DTE configuration changes and maintenance of a usage count and an in-use count in the host bridge for each cached DTE.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: International Business Machines CorporationInventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
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Publication number: 20150067297Abstract: DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.Type: ApplicationFiled: April 14, 2014Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Jesse P. Arroyo, Gregory M. Nordstrom, Srinivas Kotta, Eric N. Lais
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Publication number: 20150067224Abstract: DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Jesse P. Arroyo, Gregory M. Nordstrom, Srinivas Kotta, Eric N. Lais
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Patent number: 8918573Abstract: Embodiments of the invention relate to optimizing EDRAM refresh rates in a high performance cache architecture. A request is received from a requester to perform an operation on an I/O adapters. It is determined if the request is in a format other than a format supported by an I/O bus and if, the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus and is transmitted to the requester.Type: GrantFiled: June 23, 2010Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Thomas A. Gregg, David F. Craddock, Eric N. Lais
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Patent number: 8769180Abstract: Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system.Type: GrantFiled: November 13, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Thomas A. Gregg, David F. Craddock, Eric N. Lais
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Patent number: 8745292Abstract: A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters at I/O adapter addresses, the I/O hub including logic for implementing a method comprising receiving requests from the plurality of I/O adapters, storing the I/O adapter addresses of a requester along with their corresponding target recipient addresses and operation codes, receiving a response from a responder, the response indicating that a request has been completed, determining that the response is in a format other than a format supported by the I/O bus, transforming the response into the format supported by the I/O bus, locating a stored I/O adapter address having a corresponding target recipient address that matches the responder address and a corresponding operation code that matches the responder operation code, and transmitting the response to the stored I/O adapter address.Type: GrantFiled: June 23, 2010Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Eric N. Lais, David F. Craddock, Thomas A. Gregg
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Publication number: 20140129795Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.Type: ApplicationFiled: November 6, 2012Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: RICHARD L. ARNDT, BENJAMIN HERRENSCHMIDT, ERIC N. LAIS, STEVEN M. THURBER
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Publication number: 20140129797Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.Type: ApplicationFiled: December 3, 2013Publication date: May 8, 2014Inventors: RICHARD L. ARNDT, BENJAMIN HERRENSCHMIDT, ERIC N. LAIS, STEVEN M. THURBER
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Publication number: 20140129796Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.Type: ApplicationFiled: December 2, 2013Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais
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Patent number: 8700959Abstract: Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An aspect of the invention includes detecting an error in a communication initiated between the function and a system memory, the communication including an I/O request from an application. Future communication is prevented between the one function and the system memory in response to the detecting. The application is notified that the error in communication occurred in response to the detecting.Type: GrantFiled: November 27, 2012Date of Patent: April 15, 2014Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
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Patent number: 8650335Abstract: A measurement facility is provided for capturing and presenting fine-grained usage information for adapter functions in an input/output subsystem. Adapter specific input/output traffic is tracked on a per function basis and the results are dynamically presented to the user. This information is useful for performance tuning, load balancing and usage based charging, as examples.Type: GrantFiled: June 23, 2010Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: Frank W. Brice, Jr., David Craddock, Beth A. Glendening, Thomas A. Gregg, Eric N. Lais, Peter K. Szwed, Steven G. Wilkins
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Patent number: 8650337Abstract: Various address translation formats are available for use in obtaining system memory addresses for use by requestors in accessing system memory. The particular address translation format to be used by a given requestor, an example of which is an adapter function, is pre-registered in a device table entry associated with that requestor.Type: GrantFiled: June 23, 2010Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais, Donald W. Schmidt
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Patent number: 8645606Abstract: Embodiments of the invention relate to upbound input/output expansion requests and response processing in a PCIE architecture. A first request to perform an operation on a host system is intitiated. The first request is formatted for the first protocol and includes data that is required in order to process the first request. A second request is created in response to the first request, the second request includes a header and is formatted according to the second protocol. The data required to process the first request in the header of the second request is stored, and the second request is sent to the host system.Type: GrantFiled: June 23, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Thomas A. Gregg, David F. Craddock, Eric N. Lais
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Patent number: 8645767Abstract: Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An error is detected in a communication initiated between a function and the system memory, the communication including an I/O request from an application. Future communication between the function and the system memory is prevented in response to the detecting. The application is notified that the error in communication occurred in response to the detecting.Type: GrantFiled: June 23, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
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Patent number: 8635430Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.Type: GrantFiled: June 23, 2010Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais
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Patent number: 8631222Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.Type: GrantFiled: November 8, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais
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Patent number: 8615622Abstract: A system for implementing non-standard I/O adapters in a standardized I/O architecture, the system comprising an I/O hub communicatively coupled to an I/O bus and at least one I/O adapter, the I/O hub including logic for implementing a method, the method comprising receiving a request to perform an operation on the I/O adapter from a requester at a requester address, the I/O adapter at a destination address, determining that the request is in a format other than a format supported by the I/O bus, the I/O bus expecting a requester identifier at a first location in a header of the request, reformatting the request into the format supported by the I/O bus, the reformatting comprising storing the requester address, the destination address and an operation code at the first location in the header of the reformatted request, and sending the reformatted request to the I/O adapter.Type: GrantFiled: June 23, 2010Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Thomas A. Gregg, Gerd K. Bayer, David F. Craddock, Michael Jung, Eric N. Lais, Elke G. Nass